Patents by Inventor Xiang He

Xiang He has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170308536
    Abstract: Aspects extend to methods, systems, and computer program products for ranking contextual metadata to generate relevant data insights. Aspects of the invention can be used to enhance data analytics by automatically deriving relevance signals used to generate insights closely related to the context in which a user is exploring or analyzing data. User experiences can include embedded data visualizations, search engines, and natural language querying systems to help users understand their data more effectively. By utilizing metrics on the relevance information, insights related and/or relevant to the context in which the user is analyzing data can be created. Thus, relevance information can define a scope for a variety of automatically generated insights of data. Insight generation can be based on computed relevance signals that target areas interesting to users.
    Type: Application
    Filed: June 16, 2016
    Publication date: October 26, 2017
    Inventors: Saliha Azzam, Steven Paul Breyer, Eeshan Manish Shah, Youssef El Fassy Fihry, Ankur Satyendrakumar Sharma, Manal Hussein Alassaf, Xiang He, Vikram Rajasekaran
  • Publication number: 20170308349
    Abstract: Disclosed in an embodiment of the present invention is a multi-screen sharing based application management method and device, storage medium, the method comprising: determining whether an application is an application to be shared when the application is detected to start; obtaining a security attribute of the application if the application is determined to be the application to be shared, and sharing with a remote user the application matching the attribute value according to the attribute value of the security attribute.
    Type: Application
    Filed: January 20, 2015
    Publication date: October 26, 2017
    Inventors: Xiang He, Lei Zhang
  • Patent number: 9754655
    Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: September 5, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Mosaddiq Saifuddin, SankaraRao Kunapareddy, Keunsoo Roh, Chun Xiang He, Pratik Patel, Nicholas Ambur, Jeremy Haugen
  • Publication number: 20170250732
    Abstract: A data network for a multiple dwelling unit (MDU) enables efficient use of a MoCA (Multimedia over Coax Alliance) system. The data network includes a distribution point unit (DPU) connected to an access network, a plurality of modems in the MDU, a plurality of coaxial cables extending through the MDU between the DPU and the plurality of modems, and at least one network expander present between the DPU and a subset of the plurality of modems. The network expander can be a repeater that retransmits received signals, wherein the DPU, the plurality of modems, and the network expander exchange data via the plurality of coaxial cables using MoCA protocols.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 31, 2017
    Inventors: David B. Bowler, Bruce C. Pratt, Theodore A. Colarusso, Xiang He
  • Patent number: 9703036
    Abstract: Disclosed are structures with an optical waveguide having a first segment at a first level and a second segment extending between the first level and a higher second level and further extending along the second level. Specifically, the waveguide comprises a first segment between first and second dielectric layers. The second dielectric layer has a trench, which extends through to the first dielectric layer and which has one side positioned laterally adjacent to an end of the first segment. The waveguide also comprises a second segment extending from the bottom of the trench on the side adjacent to the first segment up to and along the top surface of the second dielectric layer on the opposite side of the trench. A third dielectric layer covers the second segment in the trench and on the top surface of the second dielectric layer. Also disclosed are methods of forming such optoelectronic structures.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhong-Xiang He, Qizhi Liu, Ronald G. Meunier, Steven M. Shank
  • Patent number: 9691623
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Patent number: 9662372
    Abstract: The present invention is related to compositions and methods to treat, ameliorate and/or prevent morbidity and/or mortality from microbial infections. In particular, bacterial infections that are associated with the production and release of bacterial toxins. For example, many Clostridia bacteria, such as Clostridium difficile, release toxins resulting in tissue and organ damage and death, even after antibiotic therapy that either reduces or eliminates the bacteria. In particular, various peptides, polypeptides, and proteins are disclosed herein that either inactivate Clostridium difficile toxin and/or reduce Clostridium difficile toxin production.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 30, 2017
    Assignee: BIOLOG, Inc.
    Inventors: Barry Bochner, Xiang-He Lei
  • Publication number: 20170148504
    Abstract: In an embodiment, a dynamic random-access memory (DRAM) system configures an inactive portion of a DRAM die to operate in accordance with a self-refresh mode that is characterized by refreshes of the DRAM die being controlled by a local DRAM die controller integrated into the DRAM die. The DRAM system also configures an active portion of the DRAM die to operate in accordance with a controller-managed refresh mode while the inactive portion of the DRAM die operates in the self-refresh mode, the controller-managed refresh mode characterized by refreshes of the DRAM die being controlled by a controller that is external to the DRAM die.
    Type: Application
    Filed: November 1, 2016
    Publication date: May 25, 2017
    Inventors: Mosaddiq SAIFUDDIN, SankaraRao KUNAPAREDDY, Keunsoo ROH, Chun Xiang HE, Pratik PATEL, Nicholas AMBUR, Jeremy HAUGEN
  • Publication number: 20170148672
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: Jeffrey P. GAMBINO, Thomas J. HARTSWICK, Zhong-Xiang HE, Anthony K. STAMPER, Eric J. WHITE
  • Patent number: 9620371
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: April 11, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Patent number: 9613853
    Abstract: Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 4, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Zhong-Xiang He, Trevor A. Thompson, Eric J. White
  • Patent number: 9524924
    Abstract: An approach to creating a semiconductor structure for a dielectric layer over a void area includes determining a location of a void area of the topographical semiconductor feature. A second dielectric layer is deposited on a first dielectric layer and a top surface of a topographical semiconductor feature. The second dielectric layer is patterned to one or more portions, wherein at least one portion of the patterned second dielectric layer is over the location of the void area of the topographical semiconductor feature. A first metal layer is deposited over the second dielectric layer, at least one portion of the first dielectric layer, and a portion of the top surface of the topographical semiconductor feature. A chemical mechanical polish of the first metal layer is performed, wherein the chemical mechanical polish reaches the top surface of at least one of the one or more portions of the second dielectric layer.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel J. Couture, Jeffrey P. Gambino, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 9483447
    Abstract: Methods and devices for adding hyperlink to text are disclosed: generating hyperlink word list and characteristic word list in advance, determining co-occurrence frequency with each hyperlink word; to each text X which to be added the hyperlink, word segmentation processing them respectively, extracting the hyperlink word occurred in the hyperlink word list and the characteristic word occurred in the characteristic word list from results of word segmentation, determining weights of each extracted hyperlink word and extracted characteristic word, getting final weights of each extracted hypertext link word according to the co-occurrence frequency of each extracted characteristic word and each extracted hyperlink word and the weights; descendingly sorting each extracted hyperlink word according to the final weights, adding hyperlink to first k hyperlink words, and K is positive integer. Applying the solution, it can improve the relativity of the added hyperlink and the text, and it is easy to implement.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: November 1, 2016
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Xiang He, Qi Bian, Feng Jiao
  • Patent number: 9478427
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: October 25, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey P. Gambino, Thomas J. Hartswick, Zhong-Xiang He, Anthony K. Stamper, Eric J. White
  • Publication number: 20160284645
    Abstract: A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.
    Type: Application
    Filed: June 10, 2016
    Publication date: September 29, 2016
    Inventors: Jeffrey P. GAMBINO, Thomas J. HARTSWICK, Zhong-Xiang HE, Anthony K. STAMPER, Eric J. WHITE
  • Patent number: 9437539
    Abstract: Structures and methods of making a dielectric region in a bulk silicon (Si) substrate of a mixed-signal integrated circuit (IC) provide a high-Q passive resonator. Deep trenches within the bulk Si substrate in <100> directions are expanded by wet etching to form contiguous cavities, which are filled by Si oxide to form a dielectric region. The dielectric region enhances the quality (Q) of an overlying passive resonator, formed in metallization layers of the mixed-signal IC.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: September 6, 2016
    Assignee: International Business Machines Corporation
    Inventors: James S. Dunn, Zhong-Xiang He, Qizhi Liu
  • Patent number: 9431789
    Abstract: In some aspects of the present application, an apparatus for producing an interference pattern on a photosensitive portion formed on a surface of a sample is disclosed. The apparatus can include an optical system for providing interference between two coherent spherical wavefronts impinging on a thin-film photosensitive material formed on a surface of a sample, wherein a plane of the surface normal of the sample is arranged at an angle with respect to a plane defined by center propagation vectors of the two coherent spherical wavefronts; and one or more actuating elements operable to actuate one or more optical elements in the optical system, the sample, or both the one or more optical elements and the sample in one or more degrees of freedom to control a relative magnitude of a longitudinal and a transverse chirp of the interference pattern.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: August 30, 2016
    Assignee: STC.UNM
    Inventors: Steven R. J. Brueck, Xiang He, Steve Benoit
  • Patent number: 9424992
    Abstract: A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: James S. Dunn, Zhong-Xiang He, Anthony K. Stamper
  • Patent number: 9406472
    Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dinh Dang, Thai Doan, George A. Dunbar, III, Zhong-Xiang He, Russell T. Herrin, Christopher V. Jahnes, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, John G. Twombly, Eric J. White
  • Patent number: 9390969
    Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: July 12, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: David A. DeMuynck, Zhong-Xiang He, Daniel R. Miga, Matthew D. Moon, Daniel S. Vanslette, Eric J. White