Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Abstract: A single-core optical transceiver is an optical transceiver for transmitting or receiving an optical signal through a single optical fiber. The single-core optical transceiver has a light emitting device for transmitting the optical signal and a light receiving device for receiving the optical signal. The light emitting device is an LED configured including a sapphire substrate arranged on a light receiving surface of the light receiving device so as to be coaxial with the light receiving surface, and a nitride semiconductor layer laid on the sapphire substrate. Even with the light emitting device being arranged on the light receiving surface of the light receiving device, the optical signal from the optical fiber can be received on the entire area of the light receiving surface, so as to adequately improve the light sensitivity.

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

Abstract: The present disclosure provides physically unclonable products and fabrication methods thereof.

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Abstract: Provided are approaches for patterning multiple, dense features in a semiconductor device using a memorization layer. Specifically, an approach includes: patterning a plurality of openings in a memorization layer; forming a gap-fill material within each of the plurality of openings; removing the memorization layer; removing an etch stop layer adjacent the gap-fill material, wherein a portion of the etch stop layer remains beneath the gap-fill material; etching a hardmask to form a set of openings above the set of gate structures, wherein the etch to the hardmask also removes the gap-fill material from atop the remaining portion of the etch stop layer; and etching the semiconductor device to remove the hardmask within each of the set of openings. In one embodiment, a set of dummy S/D contact pillars is then formed over a set of fins of the semiconductor device by etching a dielectric layer selective to the gate structures.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: The present invention provides a method and an apparatus for processing a bearer. The method includes performing depth packet inspection DPI processing on a traffic flow of a service according to a preset layer-7 protocol type matching rule. Alternatively, shallow packet inspection SPI processing is performed on a traffic flow of a service according to a preset layer-3 or layer-4 protocol type matching rule so as to obtain a DPI/SPI processing result. According to the DPI/SPI result and the preset matching rule, a service quality attribute parameter of the service is determined. The method further includes determining whether the service quality attribute parameter is the same as a service quality attribute parameter of an existing bearer, and if different, creating a dedicated bearer for the service.

Abstract: Integrated circuits with improved gate structures and methods for fabricating integrated circuits with improved gate structures are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures. A gate-forming material is deposited over the semiconductor substrate and fin structures. The method includes performing a first etch process to etch the gate-forming material to form a gate line having a first side and a second side. The first side and second side of the gate line are bounded with material. The method includes performing a second etch process to etch a portion of the gate line bound by the material to separate the gate line into adjacent gate structures and to define a tip-to-tip distance between the adjacent gate structures.

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract: Embodiments provide a policy formulating method. The method includes: receiving, by a policy server, User-Agent information sent by a gateway, where the User-Agent information carries type information of a terminal or type information of a browser used by a terminal; determining, by the policy server, a type of the terminal according to the User-Agent information; and formulating, by the policy server, a charging policy and/or a QoS quality of service policy according to the type of the terminal. Type information of a user terminal or type information a browser used by a terminal is reported to a policy server. The policy server is capable of correctly distinguishing a terminal type, for example a mobile phone or a PC is surfing the Internet, and then the policy server formulates a corresponding policy to implement Internet access charging and QoS guarantee.

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract: Embodiments of the present invention provide a data processing method, device, and system, which relate to the communications field and can perform processing according to requirements of data services of different user equipments, improve a processing effect, and enhance user experience. The method includes: obtaining, by an ADN device, an application delivery policy, and then performing, according to the application delivery policy, service processing for a data service currently running in a first user equipment. The data processing method, device, and system provided by the embodiments of the present invention are used to perform service processing for a currently running data service of a first user whose optimization is supported by the ADN device.

Abstract: The present invention provides a method and an apparatus for processing a bearer. The method includes performing depth packet inspection DPI processing on a traffic flow of a service according to a preset layer-7 protocol type matching rule. Alternatively, shallow packet inspection SPI processing is performed on a traffic flow of a service according to a preset layer-3 or layer-4 protocol type matching rule so as to obtain a DPI/SPI processing result. According to the DPI/SPI result and the preset matching rule, a service quality attribute parameter of the service is determined. The method further includes determining whether the service quality attribute parameter is the same as a service quality attribute parameter of an existing bearer, and if different, creating a dedicated bearer for the service.

Abstract: Etching a feature of a structure by an etch system is facilitated by varying supply of radio frequency (RF) power pulses to the etch system. The varying provides at least one RF power pulse, of the supplied RF power pulses, that deviates from one or more other RF power pulses, of the supplied RF power pulses, by at least one characteristic.

Abstract: The policy formulating method includes: receiving, by a policy server, User-Agent user-agent information sent by a gateway, where the User-Agent information carries type information of a terminal or type information of a browser used by a terminal; determining, by the policy server, a type of the terminal according to the User-Agent information; and formulating, by the policy server, a charging policy and/or a QoS quality of service policy according to the type of the terminal. Type information of a user terminal or type information a browser used by a terminal is reported to a policy server; the policy server is capable of correctly distinguishing a terminal type, for example a mobile phone or a PC is surfing the Internet, and then the policy server formulates a corresponding policy to implement Internet access charging and QoS guarantee.

Abstract: A non-planar semiconductor structure includes mixed n-and-p type raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon and silicon germanium, naturally growing into a diamond shape. The surface area of the epitaxial structures is increased by removing portion(s) thereof, masking each type as the other type is grown and then subsequently modified by the removal. The removal may create multi-head (e.g., dual-head) epitaxial structures, together with the neck of the respective raised structure resembling a Y-shape.

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.