Patents by Inventor Xiang Zou
Xiang Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240143361Abstract: An apparatus and method for implementing a new virtualized execution environment while supporting instructions and operations of a legacy virtualized execution environment.Type: ApplicationFiled: October 1, 2022Publication date: May 2, 2024Inventors: Tyler SONDAG, Andreas KLEEN, David SHEFFIELD, Xiang ZOU, Terry PARKS, Jason BRANDT, Ittai ANATI
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Publication number: 20240103869Abstract: Techniques for using CPUID for showing features that are deprecated are described. In some examples, CPUID is to include at least one field for an opcode, one or more fields to identify a source operand which is to store a LSL selector value, and one or more fields to identify a destination register operand, wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the first source register operand matches a LSL selector value stored in the control register, and set a flag in a flags register.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Andreas Kleen, Jason Brandt, Ittai Anati, David Sheffield, Toby Opferman, Ian Hanschen, Xiang Zou, Terry Parks
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Patent number: 11920743Abstract: An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.Type: GrantFiled: July 22, 2022Date of Patent: March 5, 2024Assignee: JIAXING SUPER LIGHTING ELECTRIC APPLIANCE CO., LTDInventors: Guang-Dong Wang, Ji-Feng Xu, Ming-Bin Wang, Zi-Xiang Zou, Dong-Mei Zhang
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Publication number: 20230385669Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventor: Xiang ZOU
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Patent number: 11803167Abstract: Disclosed are an energy service system of a multi-machine production line and a control method thereof, the method includes reorganizing respective machines in the production line into three types of controllable entities: a drive system, an energy supply bus and an execution device, equipping them with a control center, and selecting a sub-drive system that is idle and is capable of completing the work stage with high energy efficiency to supply energy service for the corresponding execution device through the energy supply bus. Further disclosed is a design method of a multi-machine shared drive system of a production line, which increases the number of basic flow units of each drive unit to a maximum value one by one, and coordinates action time to form a variety of scheduling schemes, and selects a configuration scheme whose total time and total energy consumption are less as the shared drive system.Type: GrantFiled: May 19, 2021Date of Patent: October 31, 2023Assignee: HEFEI UNIVERSITY OF TECHNOLOGYInventors: Haihong Huang, Xiang Zou, Lei Li, Libin Zhu, Zhifeng Liu
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Publication number: 20230315473Abstract: Embodiments of apparatuses and methods for variable-length instruction steering to instruction decode clusters are disclosed. In an embodiment, an apparatus includes a decode cluster and chunk steering circuitry. The decode cluster includes multiple instruction decoders. The chunk steering circuitry is to break a sequence of instruction bytes into a plurality of chunks, create a slice from a one or more of the plurality of chunks based on one or more indications of a number of instructions in each of the one or more of the plurality of chunks, wherein the slice has a variable size and includes a plurality of instructions, and steer the slice to the decode cluster.Type: ApplicationFiled: April 2, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Muhammad Azeem, Rangeen Basu Roy Chowdhury, Xiang Zou, Malihe Ahmadi, Joju Joseph Zajo, Ariel Sabba, Ammon Christiansen, Polychronis Xekalakis, Eliyah Kilada
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Patent number: 11748649Abstract: Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.Type: GrantFiled: December 13, 2019Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Xiang Zou, Justin Hogaboam, Adam Holmes, Sonika Johri
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Patent number: 11748651Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.Type: GrantFiled: November 17, 2022Date of Patent: September 5, 2023Assignee: Intel CorporationInventor: Xiang Zou
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Publication number: 20230244459Abstract: Apparatus and method for compiling and executing hybrid classical-quantum programs. For example, one embodiment of a method comprises: reading source code specifying both non-quantum operations to be performed by a host processor and quantum operations to be performed by a quantum accelerator; compiling the source code to generate a target object file, wherein portions of the source code specifying the quantum operations are compiled into quantum basic blocks (QBBs) in the target object file, each QBB comprising one or more quantum instructions to be executed by the quantum accelerator and wherein portions of the source code specifying the non-quantum operations are compiled into native instructions to be executed by the host processor.Type: ApplicationFiled: January 31, 2022Publication date: August 3, 2023Inventors: XIANG ZOU, JUSTIN HOGABOAM, PRADNYA LAXMAN KHALATE, XIN-CHUAN WU, ANNE MATSUURA, SHAVINDRA PREMARATNE
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Patent number: 11704588Abstract: Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.Type: GrantFiled: September 27, 2018Date of Patent: July 18, 2023Assignee: Intel CorporationInventors: Xiang Zou, Justin Hogaboam
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Patent number: 11681533Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.Type: GrantFiled: June 17, 2019Date of Patent: June 20, 2023Assignee: Intel CorporationInventors: Ron Gabor, Alaa Alameldeen, Abhishek Basak, Fangfei Liu, Francis McKeen, Joseph Nuzman, Carlos Rozas, Igor Yanover, Xiang Zou
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Publication number: 20230175653Abstract: An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.Type: ApplicationFiled: July 22, 2022Publication date: June 8, 2023Inventors: Guang-Dong Wang, Ji-Feng Xu, Ming-Bin Wang, Zi-Xiang Zou, Dong-Mei Zhang
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Publication number: 20230168397Abstract: This disclosure provides an area array detector, a detection method, and a corresponding container/vehicle inspection system, and relates to the field of ray scanning. The area array detector for the container/vehicle inspection system includes sparsely arranged detector assemblies, and a first detector assembly is different from other second detector assemblies; and a backplane for carrying and mounting detector assemblies, and the area array detector supporting scanning modes is enabled.Type: ApplicationFiled: November 27, 2022Publication date: June 1, 2023Inventors: Linxia TAN, Hao Yu, Xiang Zou, Weibin Zhu, Junxiao Wang
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Patent number: 11599818Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.Type: GrantFiled: December 13, 2019Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Xiang Zou, Shavindra Premaratne
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Publication number: 20230016817Abstract: Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.Type: ApplicationFiled: June 26, 2021Publication date: January 19, 2023Inventors: Shavindra PREMARATNE, Albert SCHMITZ, Anne MATSUURA, Xiang ZOU
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Patent number: 11550977Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.Type: GrantFiled: January 29, 2019Date of Patent: January 10, 2023Assignee: INTEL CORPORATIONInventors: Sahar Daraeizadeh, Anne Matsuura, Xiang Zou, Sonika Johri
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Patent number: 11531922Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.Type: GrantFiled: September 27, 2018Date of Patent: December 20, 2022Assignee: Intel CorporationInventor: Xiang Zou
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Publication number: 20220206818Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Alaa Alameldeen, Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207148Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207154Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Richard Winterton, Mohammad Reza Haghighat, Asit Mallick, Alaa Alameldeen, Abhishek Basak, Jason W. Brandt, Michael Chynoweth, Carlos Rozas, Scott Constable, Martin Dixon, Matthew Fernandez, Fangfei Liu, Francis McKeen, Joseph Nuzman, Gilles Pokam, Thomas Unterluggauer, Xiang Zou