Abstract: Apparatus and method for injected spin echo sequences in a quantum processor. For example, one embodiment of a processor includes a decoder to decode quantum instructions to generate quantum microoperations (uops) and to decode non-quantum instructions to generate non-quantum uops, execution circuitry to execute the quantum uops and non-quantum uops, and a corrective sequence data structure to identify and/or store corrective sets of uops for one or more of the quantum instructions. The decoder is to query the corrective sequence data structure upon receiving a first quantum instruction to determine if one or more corrective uops exist, and if the one or more corrective uops exist, the decoder is to submit the one or more corrective uops for execution by the execution circuitry.

Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.

Abstract: An LED tube lamp includes a first and second members and a connection member. Each of the first and second members includes lighting part and an end part. Each lighting part includes LED light strip. The connection member includes electrical connection portions and joining portions for the first and second members. The connection member connects the first member with the second member by the joining portions and the electrical connection portions and makes the first member substantially coaxial to the second member.

Abstract: This disclosure provides an area array detector, a detection method, and a corresponding container/vehicle inspection system, and relates to the field of ray scanning. The area array detector for the container/vehicle inspection system includes sparsely arranged detector assemblies, and a first detector assembly is different from other second detector assemblies; and a backplane for carrying and mounting detector assemblies, and the area array detector supporting scanning modes is enabled.

Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

Abstract: Apparatus and method for actively mitigating coherent errors by modifying an original quantum circuit, inserting Clifford gate operations at intermediate stages. Embodiments of the apparatus and method may perform CGI statically, at the compiling stage, and/or dynamically, at the control processing stage. The insertion of Clifford gates takes advantage of the symmetries in a quantum circuit and actively cancels coherent errors, maintaining the quantum processor in a state as close as possible to the original tune-up environment.

Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

Abstract: An apparatus and method for scalable qubit addressing. For example, one embodiment of a processor comprises: a decoder comprising quantum instruction decode circuitry to decode quantum instructions to generate quantum microoperations (uops) and non-quantum decode circuitry to decode non-quantum instructions to generate non-quantum uops; execution circuitry comprising: an address generation unit (AGU) to generate a system memory address responsive to execution of one or more of the non-quantum uops; and quantum index generation circuitry to generate quantum index values responsive to execution of one or more of the quantum uops, each quantum index value uniquely identifying a quantum bit (qubit) in a quantum processor; wherein to generate a first quantum index value for a first quantum uop, the quantum index generation circuitry is to read the first quantum index value from a first architectural register identified by the first quantum uop.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.

Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.

Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (?op) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing ?op. Other embodiments are described and claimed.

Abstract: Disclosed are an energy service system of a multi-machine production line and a control method thereof, the method includes reorganizing respective machines in the production line into three types of controllable entities: a drive system, an energy supply bus and an execution device, equipping them with a control center, and selecting a sub-drive system that is idle and is capable of completing the work stage with high energy efficiency to supply energy service for the corresponding execution device through the energy supply bus. Further disclosed is a design method of a multi-machine shared drive system of a production line, which increases the number of basic flow units of each drive unit to a maximum value one by one, and coordinates action time to form a variety of scheduling schemes, and selects a configuration scheme whose total time and total energy consumption are less as the shared drive system.

Abstract: An apparatus and method for non-speculative resource deallocation.

Abstract: Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.

Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

Abstract: Parallel streaming apparatus and method for parallel quantum computations.