Patents by Inventor Xiang Zou

Xiang Zou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220207148
    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
  • Publication number: 20220207146
    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
  • Publication number: 20220207147
    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
  • Publication number: 20220207138
    Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.
    Type: Application
    Filed: December 26, 2020
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
  • Publication number: 20220091851
    Abstract: In one embodiment, a processor includes: a decode circuit to decode a load instruction that is to load an operand to a destination register, the decode circuit to generate at least one fencing micro-operation (?op) associated with the destination register; and a scheduler circuit coupled to the decode circuit. The scheduler circuit is to prevent speculative execution of one or more instructions that consume the operand in response to the at least one fencing ?op. Other embodiments are described and claimed.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Inventors: FANGFEI LIU, ALAA ALAMELDEEN, ABHISHEK BASAK, SCOTT CONSTABLE, FRANCIS MCKEEN, JOSEPH NUZMAN, CARLOS ROZAS, THOMAS UNTERLUGGAUER, XIANG ZOU
  • Publication number: 20210271216
    Abstract: Disclosed are an energy service system of a multi-machine production line and a control method thereof, the method includes reorganizing respective machines in the production line into three types of controllable entities: a drive system, an energy supply bus and an execution device, equipping them with a control center, and selecting a sub-drive system that is idle and is capable of completing the work stage with high energy efficiency to supply energy service for the corresponding execution device through the energy supply bus. Further disclosed is a design method of a multi-machine shared drive system of a production line, which increases the number of basic flow units of each drive unit to a maximum value one by one, and coordinates action time to form a variety of scheduling schemes, and selects a configuration scheme whose total time and total energy consumption are less as the shared drive system.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventors: Haihong HUANG, Xiang ZOU, Lei LI, Libin ZHU, Zhifeng LIU
  • Publication number: 20210200552
    Abstract: An apparatus and method for non-speculative resource deallocation.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: FANGFEI LIU, CARLOS ROZAS, THOMAS UNTERLUGGAUER, FRANCIS MCKEEN, ALAA ALAMELDEEN, Abhishek Basak, XIANG ZOU, RON GABOR, JIYONG YU
  • Publication number: 20210182725
    Abstract: Apparatus and method for performing a quantum rotation operation. For example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (FP) value and to store the FP value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the FP value from the first register and compress the FP value to generate a compressed FP value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed FP value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: XIANG ZOU, SHAVINDRA PREMARATNE
  • Publication number: 20210182724
    Abstract: Apparatus and method for specifying quantum operation parallelism. For example, one embodiment of an apparatus comprises: instruction fetch circuitry to fetch a plurality of quantum instructions from a memory or a cache; slice-based instruction processing circuitry to identify quantum circuit slices comprising sets of one or more of the plurality of quantum instructions; and one or more instruction decoders to decode the quantum instructions to generate quantum microoperations; and quantum execution circuitry to execute sets of the quantum microoperations in parallel based on the quantum circuit slices.
    Type: Application
    Filed: December 13, 2019
    Publication date: June 17, 2021
    Inventors: XIANG ZOU, JUSTIN HOGABOAM, ADAM HOLMES, SONIKA JOHRI
  • Publication number: 20210173660
    Abstract: Parallel streaming apparatus and method for parallel quantum computations.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: JUSTIN HOGABOAM, XIANG ZOU, SHAVINDRA PREMARATNE, NADER KHAMMASSI
  • Patent number: 11010166
    Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debabrata Mohapatra, Perry H. Wang, Xiang Zou, Sang Kyun Kim, Deepak A. Mathaikutty, Gautham N. Chinya
  • Patent number: 10972264
    Abstract: A method is provided that protects electronic Identity information based on key derived operation. The method includes using an electronic Identity server to send an application derived identifier of the application and user electronic Identity code to a host security module that randomly generates an application master key, encrypts the application derived identifier with the application master key, and gets an application encryption key. The host security module encrypts the user electronic Identity code with the application encryption key, and gets an encryption document. The electronic Identity server codes the encryption document and an application identity code, and gets an application electronic Identity code. The electronic Identity server uses the application electronic Identity code as the user identifier.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: April 6, 2021
    Assignee: THE THIRD INSTITUTE OF THE MINISTRY OF PUBLIC SECURITY
    Inventors: Xiang Zou, Minghui Yang, Lishun Ni, Yixin Xu, Jun Huang
  • Patent number: 10935691
    Abstract: The present disclosure relates to the technical field of CT detection, and in particular to a CT inspection system and a CT imaging method. The CT inspection system provided by the present disclosure comprises a radioactive source device, a detection device, a rotation monitoring device and an imaging device, wherein the detection device obtains detection data at a frequency that is N times a beam emitting frequency of the radioactive source device; the rotation monitoring device detects a rotation angle of the detection device and transmits a signal to the imaging device each time the detection device rotates by a preset angle; the imaging device determines a rotational position of the detection device each time the radioactive source device emits a beam according to the signal transmitted by the rotation monitoring device and the detection data of the detection device.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 2, 2021
    Inventors: Kejun Kang, Jianmin Li, Xiulin Ni, Yulan Li, Yuanjing Li, Zhiqiang Chen, Li Zhang, Liang Li, Xiang Zou, Weifeng Yu, Hejun Zhou, Chunguang Zong
  • Publication number: 20200410094
    Abstract: Embodiments of methods and apparatuses for hardware load hardening are disclosed. In an embodiment, a processor includes safe logic, data forwarding hardware, and data fetching hardware. The safe logic is to determine whether a load is safe. The data forwarding hardware is to, in response to a determination that the load is safe, forward data requested by the load. The data fetching logic is to fetch the data requested by the load, regardless of the determination that the load is safe.
    Type: Application
    Filed: June 29, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Fangfei Liu, Alaa Alameldeen, Abhishek Basak, Ron Gabor, Francis McKeen, Joseph Nuzman, Carlos Rozas, Igor Yanover, Xiang Zou
  • Patent number: 10877910
    Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Hong Wang, Per Hammarlund, Xiang Zou, John P. Shen, Xinmin Tian, Milind Girkar, Perry H. Wang, Piyush N. Desai
  • Patent number: 10809394
    Abstract: The present disclosure provides a dual-energy detection apparatus and method. The dual-energy detection apparatus includes an X-ray source configured to send a first X-ray beam to an object to be measured; a scintillation detector configured to work in an integration mode, and receive a second X-ray beam penetrating through the object to be measured to generate a first electrical signal; a Cherenkov detector configured to be located behind the scintillation detector, work in a counting mode, and receive a third X-ray beam penetrating through the scintillation detector to generate a second electrical signal; and a processor configured to output image, thickness and material information of the object to be measured according to the first electrical signal and the second electrical signal. The dual-energy detection method provided by the present disclosure may acquire an image of the object to be measured that is clearer and contains more information.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 20, 2020
    Assignee: NUCTECH COMPANY LIMITED
    Inventors: Shuwei Li, Qingjun Zhang, Xiang Zou, Bozhen Zhao, Junxiao Wang, Weibin Zhu, Yongqiang Wang, Wenjian Zhang
  • Publication number: 20200313882
    Abstract: A method is provided that protects electronic Identity information based on key derived operation. The method includes using an electronic Identity server to send an application derived identifier of the application and user electronic Identity code to a host security module that randomly generates an application master key, encrypts the application derived identifier with the application master key, and gets an application encryption key. The host security module encrypts the user electronic Identity code with the application encryption key, and gets an encryption document. The electronic Identity server codes the encryption document and an application identity code, and gets an application electronic Identity code. The electronic Identity server uses the application electronic Identity code as the user identifier.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Applicant: THE THIRD INSTITUTE OF THE MINISTRY OF PUBLIC SECURITY
    Inventors: Xiang Zou, Minghui Yang, Lishun Ni, Yixin Xu, Jun Huang
  • Patent number: 10775320
    Abstract: The present disclosure discloses an afterglow detection device and an afterglow detection method. The afterglow detection device comprises: an X-ray tube for emitting an X-ray beam; a first reading circuit for receiving a first detected signal from a to-be-detected detector to form and output a first measurement signal according to the first detected signal, the to-be-detected detector being connected to the first reading circuit and disposed on a beam-out side of the X-ray tube to receive radiation of the X-ray beam and outputting the first detected signal to the first reading circuit at the time of detection; a residual ray detector disposed on a beam-out side of the X-ray tube; a second reading circuit connected to the residual ray detector for receiving a second detected signal from the residual ray detector to form and output a second measurement signal according to the second detected signal.
    Type: Grant
    Filed: May 5, 2019
    Date of Patent: September 15, 2020
    Assignee: NUCTECH COMPANY LIMITED
    Inventors: Shuwei Li, Wenjian Zhang, Xiang Zou, Bozhen Zhao, Qingjun Zhang, Huishao He, Yongqiang Wang, Yanchun Wang
  • Publication number: 20200272474
    Abstract: Embodiments of methods and apparatuses for restricted speculative execution are disclosed. In an embodiment, a processor includes configuration storage, an execution circuit, and a controller. The configuration storage is to store an indicator to enable a restricted speculative execution mode of operation of the processor, wherein the processor is to restrict speculative execution when operating in restricted speculative execution mode. The execution circuit is to perform speculative execution. The controller to restrict speculative execution by the execution circuit when the restricted speculative execution mode is enabled.
    Type: Application
    Filed: June 17, 2019
    Publication date: August 27, 2020
    Applicant: Intel Corporation
    Inventors: Ron Gabor, Alaa Alameldeen, Abhishek Basak, Fangfei Liu, Francis McKeen, Joseph Nuzman, Carlos Rozas, Igor Yanover, Xiang Zou
  • Publication number: 20200242208
    Abstract: Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Sahar Daraeizadeh, Anne Matsuura, Xiang Zou, Sonika Johri