Patents by Inventor XiangNan Zhao
XiangNan Zhao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230020789Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Changhyun LEE, Xiangnan ZHAO, Haibo LI
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Publication number: 20220359021Abstract: A memory device includes a memory array including memory strings, each memory string comprising a plurality of first memory cells, a plurality of second memory cells, and one or more dummy memory cells between the first memory cells and the second memory cells. The first memory cells are between drain terminals of the memory strings and the dummy memory cells, and the second memory cells are between source terminals of the memory strings and the dummy memory cells. The bit lines are respectively coupled to drain terminals of the memory strings. The word lines are respectively coupled to gate terminals of the first memory cells and the second memory cells. A word line driver is configured to apply a first voltage signal to each of the word lines that are coupled to the gate terminals of the first memory cells during a pre-charge phase.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Xinlei Jia, Shan Li, Yali Song, Lei Jin, Hongtao Liu, Jianquan Jia, XiangNan Zhao, Yuan-Yuan Min
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Publication number: 20220359022Abstract: A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.Type: ApplicationFiled: July 22, 2022Publication date: November 10, 2022Inventors: Yali Song, Xiangnan Zhao, Yuanyuan Min, Jianquan Jia, Kaikai You
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Patent number: 11468957Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.Type: GrantFiled: March 4, 2021Date of Patent: October 11, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Changhyun Lee, Xiangnan Zhao, Haibo Li
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Patent number: 11423995Abstract: A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.Type: GrantFiled: February 26, 2021Date of Patent: August 23, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Yali Song, Xiangnan Zhao, Yuanyuan Min, Jianquan Jia, Kaikai You
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Patent number: 11398284Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.Type: GrantFiled: February 19, 2021Date of Patent: July 26, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Xinlei Jia, Shan Li, Yali Song, Lei Jin, Hongtao Liu, Jianquan Jia, XiangNan Zhao, Yuan-Yuan Min
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Publication number: 20220215888Abstract: A 3D memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second memory layers. The 3D memory device may include a plurality of NAND memory strings each extending through the first and second set of memory layers and the first dummy memory layer. The 3D memory device may include a word line (WL) driving circuit that, when programming one of the first set of memory layers, may be configured to apply a second pre-charge voltage to the first dummy memory layer during the pre-charge period. The second pre-charge voltage may overlap with the first pre-charge voltage and ramp down prior to the first pre-charge voltage.Type: ApplicationFiled: February 26, 2021Publication date: July 7, 2022Inventors: Yali Song, Xiangnan Zhao, Yuanyuan Min, Jianquan Jia, Kaikai You
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Publication number: 20220215883Abstract: A three-dimensional (3D) memory device may include a first set of memory layers, a second set of memory layers above the first set of memory layers, and a first dummy memory layer between the first and second sets of memory layers. The 3D memory device may further include a peripheral circuit that includes a word line (WL) driving circuit configured to when programming a first memory layer of the first set of memory layers, apply a first pre- charge voltage to the first dummy memory layer during a pre-charge period associated with the first memory layer, and when programming a second memory layer of the first set of memory layers located above the first memory layer, apply a second pre-charge voltage to the first dummy memory layer during a pre-charge period associated with the second memory layer. The first pre-charge voltage may be larger than the second pre-charge voltage.Type: ApplicationFiled: February 26, 2021Publication date: July 7, 2022Inventors: Yali Song, Xiangnan Zhao, Yuanyuan Min, Kaikai You
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Publication number: 20220189566Abstract: In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.Type: ApplicationFiled: March 4, 2021Publication date: June 16, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Changhyun LEE, Xiangnan ZHAO, Haibo LI
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Publication number: 20220165741Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.Type: ApplicationFiled: January 4, 2022Publication date: May 26, 2022Inventors: Xuezhun Xie, Yali Song, Lei Jin, Xiangnan Zhao, Yuanyuan Min, Jianquan Jia
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Publication number: 20220028465Abstract: A memory includes a first deck including a first set of word lines, a second deck above the first deck and including a second set of word lines, and a controller. The controller is configured to apply a program voltage to a first target word line of the first set of word lines in the first deck, and apply a first pass voltage to at least one of the first set of word lines that is below the first target word line when applying the program voltage to the first target word line. The controller is also configured to apply the program voltage to a second target word line of the second set of word lines in the second deck, and apply a second pass voltage to at least one of the second set of word lines that is below the second target word line when applying the program voltage to the second target word line. The second pass voltage is greater than the first pass voltage.Type: ApplicationFiled: October 11, 2021Publication date: January 27, 2022Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Publication number: 20210407599Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.Type: ApplicationFiled: September 10, 2021Publication date: December 30, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Patent number: 11195590Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.Type: GrantFiled: March 24, 2020Date of Patent: December 7, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Publication number: 20210249091Abstract: A memory includes a first portion, a second portion and a controller. The first portion includes a first word line to a kth word line. The second portion is formed above the first portion and includes a (k+1)th word line to an mth word line. When an xth word line is used to perform a program operation, the controller is used to apply a first voltage to the first word line to an (x?2)th word line, a second voltage to an (x?1)th word line, and a third voltage to an (x+1)th word line. x, k and m are positive integers.Type: ApplicationFiled: March 24, 2020Publication date: August 12, 2021Inventors: Yali Song, XiangNan Zhao, Ying Cui
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Publication number: 20210193237Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.Type: ApplicationFiled: February 26, 2021Publication date: June 24, 2021Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
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Publication number: 20210174885Abstract: A memory device includes a memory array including memory strings. Each memory string includes a plurality of top memory cells, a plurality of bottom memory cells, and one or more dummy memory cells between the top memory cells and the bottom memory cells. The memory device also includes a plurality of word lines respectively coupled to gate terminals of the top memory cells and the bottom memory cells. The memory device further includes a control circuit configured to provide a control signal to control programming a target memory cell of the top memory cells. The gate terminal of the target memory cell are coupled to a selected word line of the word lines.Type: ApplicationFiled: February 19, 2021Publication date: June 10, 2021Inventors: Xinlei Jia, Shan Li, Yali Song, Lei Jin, Hongtao Liu, Jianquan Jia, XiangNan Zhao, Yuan-Yuan Min
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Publication number: 20210158880Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.Type: ApplicationFiled: February 1, 2021Publication date: May 27, 2021Inventors: XiangNan Zhao, Yali Song, An Zhang, Hongtao Liu, Lei Jin
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Patent number: 10991438Abstract: A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.Type: GrantFiled: February 24, 2020Date of Patent: April 27, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Yali Song, Jianquan Jia, Kaikai You, An Zhang, XiangNan Zhao, Ying Cui, Shan Li, Kaiwei Li, Lei Jin, Xueqing Huang, Meng Lou, Jinlong Zhang
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Patent number: 10957409Abstract: A method of performing a programming operation to a three dimensional (3D) NAND memory device is disclosed. The method makes residual electrons trapped in storage regions of middle dummy memory cells of an unselected string of the 3D NAND memory device to be removed during the pre-charging phase, so as to reduce program disturb to an selected string which neighbors the unselected string.Type: GrantFiled: February 17, 2020Date of Patent: March 23, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xinlei Jia, Shan Li, Yali Song, Lei Jin, Hongtao Liu, Jianquan Jia, XiangNan Zhao, Yuan-Yuan Min
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Patent number: 10943665Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.Type: GrantFiled: December 2, 2019Date of Patent: March 9, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: XiangNan Zhao, Yali Song, An Zhang, Hongtao Liu, Lei Jin