Abstract: A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Abstract: A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

Abstract: A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.

Abstract: A method for manufacturing a fan-out panel level packaging structure includes preparing a panel level frame having a first dielectric layer and a through-cavity surrounded by the first dielectric layer, wherein the frame includes first and second surfaces, and a heat dissipation copper post extending through the first dielectric layer and exposed to the first surface, mounting a device in the through-cavity with a terminal face of the device flush with the second surface and the terminal face including a first terminal and a second terminal; forming a second dielectric layer overlying the device on the first surface, forming a first rewiring layer on the second surface, and forming a third dielectric layer on the first rewiring layer, and forming a second rewiring layer on the third dielectric layer. The second rewiring layer may be in conductive connection with the first rewiring layer.

Abstract: Provided are a data transmission method and apparatus, and a storage medium. The method includes: receiving second downlink control information over a second search space, and rejecting receiving first downlink control information over a first search space; wherein the second downlink control information comprises downlink control information for carrying feedback of a base station.

Abstract: Systems and techniques are provided for detecting a translucent matter based on light detection and ranging (LIDAR) returns. An example method can include receiving at least two LIDAR returns associated with a LIDAR beam transmitted by a LIDAR device. The two LIDAR returns include a primary return comprising a first portion of the LIDAR beam reflected from a matter and a secondary return comprising a second portion of the LIDAR beam reflected from additional matter. The example method can further include determining a distance difference between a first position of the matter along the first path and a second position of the additional matter along the second path, comparing the distance difference with a threshold, and based on the comparison between the distance difference and the threshold, determining whether the additional matter is a non-translucent matter or a translucent matter.

Abstract: Disclosed are a communication method, a network device, and a storage medium. The method may include receiving a first reference signal sent by a second UE, and acquiring a first signal strength measurement value according to the first reference signal; receiving a second reference signal sent by a BS equipment, and acquiring a second signal strength measurement value according to the second reference signal; acquiring measurement information according to the first and second signal strength measurement values, and sending the measurement information to the first BS equipment, to instruct the first BS equipment to obtain a SINR through the measurement information, and to generate a scheduling command according to the SINR; and receiving the scheduling command sent by the first BS equipment, and performing communication according to the scheduling command.

Abstract: A multi-device graded embedding package substrate includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer includes a first conductive copper pillar layer and a first device cavity. The second dielectric layer includes a first wiring layer located in a lower surface of the second dielectric layer, a second conductive copper pillar layer and a heat dissipation copper block layer provided on the first wiring layer. The third dielectric layer includes a second wiring layer, a third conductive copper pillar layer provided on the second wiring layer. A first device is attached to the bottom of the first device cavity, and a terminal of the first device is in conductive connection with the second wiring layer. A second device is attached to the bottom of a second device cavity penetrating through the first, second and third dielectric layers.

Abstract: A system and method for allocating network resources are disclosed herein. In one embodiment, the system and method are configured to perform: receiving a resource allocation message indicative of a plurality of resource groups allocated for a signal; and transmitting the signal using a portion of the plurality of resource groups, wherein, in a frequency domain, the portion of the plurality of resource groups presents a hopping pattern comprising at least a first hopping path that is associated with a first plurality of increasing frequency spacings and a second hopping path that is associated with a second plurality of decreasing frequency spacings.

Abstract: Disclosed is an embedded chip package, comprising at least one chip and a frame surrounding the at least one chip, the chip having a terminal face and a back face separated by a height of the chip, the frame having a height equal to or larger than the height of the chip, wherein the gap between the chip and the frame is fully filled with a photosensitive polymer dielectric, the terminal face of the chip being coplanar with the frame, a first wiring layer being formed on the terminal face of the chip and a second wiring layer being formed on the back face of the chip. Moreover, a method for manufacturing an embedded chip package is disclosed.

Abstract: A side-exposed embedded trace substrate includes a dielectric layer, a first wiring layer and a first wiring layer embedded in the dielectric layer. An outer surface of the first wiring layer is not higher than a surface of the dielectric layer, and the first wiring layer includes a pad having a groove to increase a side-exposed area of the pad. The contact area between the substrate and the solder during package welding is increased so that the welding reliability is enhanced, the problem of poor welding or poor reliability caused by trace embedding may be avoided, and poor filling of the packaging material due to insufficient gap between the device and the pad during packaging may be prevented.

Abstract: An embedded magnetic device integrated structure includes a first insulating layer, a first wiring layer provided on a first surface of the first insulating layer, an element and a magnetic device respectively embedded in the first insulating layer, and a terminal of the element and an electrode of the magnetic device are respectively connected to the first wiring layer, and a second wiring layer provided on a second surface of the first insulating layer and in conductive communication with the first wiring layer via a first conducting post penetrating the first insulating layer. At least one terminal of the element is in conductive communication with at least one electrode of the magnetic device through the first wiring layer.

Abstract: An embedded magnet frame, an integrated structure and a manufacturing method are disclosed. The manufacturing method includes: manufacturing conductive metal columns, a first sacrificial block and a second sacrificial block on a surface of a bearing plate; laminating a first dielectric layer on the surface of the bearing plate so that the first dielectric layer covers the conductive metal columns, the first sacrificial block and the second sacrificial block; thinning the first dielectric layer to expose surfaces of the conductive metal columns, the first sacrificial block and the second sacrificial block; etching the first sacrificial block and the second sacrificial block to form corresponding first and second mounting cavities, the second mounting cavity being used for mounting a chip; filling the first mounting cavity with magnetic slurry to form an embedded magnet; and removing the bearing plate to form an embedded magnet frame.

Abstract: A manufacturing method for a metal frame chip embedded packaging substrate includes preparing a metal plate, forming a metal frame surrounding a cavity by penetrating the metal plate, and selectively partially etching a first surface of the metal frame to form a first groove on the metal frame, embedding a chip in the cavity so that a patterned side of the chip faces the first surface, and laminating a dielectric layer on a second surface of the metal frame opposite the first surface, the dielectric layer covering a back side of the chip and filling the first groove, forming a blind hole and a window on the dielectric layer, and forming a first wiring layer on the first surface and a second wiring layer on the second surface, the first wiring layer being connected to a terminal of the chip.

Abstract: A manufacturing method for an organic interposer structure includes (a) providing a bearing plate, (b) applying a temporary bonding layer on the bearing plate, (c) applying a photosensitive dielectric layer on the temporary bonding layer, (d) forming a window on the photosensitive dielectric layer and performing metallization to form a circuit layer, (e) repeating the steps (c) and (d) on the circuit layer until the target number of layers is achieved, (f) de-bonding the temporary bonding layer and removing the bearing plate to expose the conducting post, (g) thinning the exposed conducting post to form a first pad, forming a solder mask layer on the surface of the outermost exposed circuit layer, wherein the solder mask layer exposes part of the circuit layer to form a second pad, and (h) performing a metal surface treatment on the first and second pads.

Abstract: Disclosed are a heat dissipation-electromagnetic shielding embedded packaging structure, a manufacturing method thereof, and a substrate. The heat dissipation-electromagnetic shielding embedded packaging structure includes: a dielectric layer including an upper surface and a lower surface, wherein at least one hollow cavity unit is disposed inside the dielectric layer; an insulating layer disposed in the hollow cavity unit, wherein the hollow cavity unit is partially filled with the insulating layer; an electronic element, wherein one end is embedded in the insulating layer, the other end is exposed in the hollow cavity unit, and the electronic element includes terminals; a through hole penetrating through the upper surface and the lower surface of the dielectric layer and communicating with the terminals; and a metal layer covering the six surfaces of the dielectric layer and the interior of the through hole to form a shielding layer and circuit layer respectively.

Abstract: A package carrier plate with an embedded efficient heat dissipation module and a manufacturing method therefor are disclosed. The package carrier plate with an embedded efficient heat dissipation module includes: a metal carrier plate, in which a first opening frame is provided; and a metal heat dissipation module, where the metal heat dissipation module includes a first metal layer and a second metal layer, a plurality of copper walls arranged in parallel are connected between the first metal layer and the second metal layer, a phase change material is filled in a cavity formed between every two adjacent copper walls, the metal heat dissipation module is embedded in the first opening frame, and a first dielectric layer is filled in a gap between the metal heat dissipation module and an inner side wall of the first opening frame.

Abstract: An embedded and packaged heat dissipation structure and a manufacturing method therefor, and a semiconductor are disclosed. The method includes: forming a first semi-finished plate; forming a heat dissipation plate based on the first metal layer; manufacturing a heat dissipation copper column on the heat dissipation plate; providing a dielectric layer; laminating a second metal layer on the dielectric layer; partially etching the second metal layer and the dielectric layer to form a microchannel; manufacturing a thin metal layer to enable an inner wall of the microchannel to form an isolation layer with an integrated structure to obtain a second semi-finished plate; manufacturing a first cover layer; and laminating the first cover layer and the second semi-finished plate to connect the first cover layer and the isolation layer in a sealed manner to obtain the embedded and packaged heat dissipation structure.

Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.

Abstract: A method for manufacturing an embedded package structure having an air resonant cavity according to an embodiment includes manufacturing a first substrate including a first insulating layer, a chip embedded in the insulating layer, and a wiring layer on a terminal face of the chip of the first substrate, wherein the wiring layer is provided thereon with an opening revealing the terminal face of the chip; manufacturing a second substrate which comprises a second insulating layer; locally applying a first adhesive layer on the wiring layer such that the opening revealing the terminal face of the chip is not covered; and applying a second adhesive layer on the second substrate; and attaching and curing the first adhesive layer of the first substrate and the second adhesive layer of the second substrate to obtain an embedded package structure having an air resonant cavity on the terminal face of the chip.