Patents by Inventor Xianming Chen

Xianming Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11822121
    Abstract: A cavity substrate may have a directional optoelectronic transmission channel. The cavity substrate includes a support frame, a first dielectric layer on a first surface of the support frame, and a second dielectric layer on a second surface of the support frame. The support frame, the first dielectric layer and the second dielectric layer constitute a closed cavity having an opening on one side in the length direction of the substrate, a first circuit layer is arranged on the inner surface of the first dielectric layer facing the cavity, an electrode connected with an optical communication device is arranged on the first circuit layer, the electrode is electrically conducted with the first circuit layer, a second circuit layer is arranged on the outer surfaces of the first dielectric layer and the second dielectric layer, and the first circuit layer and the second circuit layer are communicated through a via column.
    Type: Grant
    Filed: January 6, 2023
    Date of Patent: November 21, 2023
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Lei Feng, Benxia Huang, Wenshi Wang, Lina Jiang
  • Publication number: 20230369167
    Abstract: A liquid circulating cooling package substrate includes a circulating cooling structure including a cooling chamber in a first dielectric layer to expose a heat dissipation face, a metal heat dissipation layer on the inner surface of the cooling chamber, an upright support column formed on a metal heat dissipation layer, and a cooling cover supported on the support column to close the cooling chamber along the periphery of the cooling chamber. The metal heat dissipation layer completely covers the heat dissipation face and the inner side surface of the cooling chamber, and a liquid inlet and a liquid outlet are formed on the cooling cover. A circulating cooling structure is provided in the first dielectric layer, and the circulating cooling structure is formed during the processing of an embedded package substrate such that the processing flow is simple and the cost is low.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 16, 2023
    Inventors: Xianming CHEN, Juchen HUANG, Xiaowei XU, Benxia HUANG, Gao HUANG
  • Publication number: 20230361058
    Abstract: A manufacturing method for a substrate embedded with integrated inductor includes: providing a bearing plate; manufacturing a first conduction copper column on the bearing plate; arranging a first dielectric layer on the bearing plate which covers the first conduction copper column; opening the first dielectric layer to form a first opening; filling a magnetic material at the first opening; grinding the first dielectric layer so that surfaces of the first conduction copper column and the magnetic material are flush with a surface of the first dielectric layer; removing the bearing plate, etching a metal layer on the surface of the first dielectric layer to form a package substrate; arranging a first circuit layer and a solder mask layer on an upper surface and a lower surface of the package substrate; and forming a window in the solder mask layer corresponding to the first circuit layer.
    Type: Application
    Filed: February 27, 2023
    Publication date: November 9, 2023
    Inventors: Xianming CHEN, Xiaowei XU, Juchen HUANG, Benxia HUANG, Gao HUANG
  • Publication number: 20230326765
    Abstract: A package substrate manufacturing method includes: providing a bearing plate, manufacturing a pattern and depositing metal to form the first circuit layer; manufacturing a pattern on the first circuit layer, depositing and etching metal to form a metal cavity, laminating a dielectric layer on the metal cavity, and performing thinning to expose the metal cavity; removing the bearing plate, etching the metal cavity to expose the cavity, depositing metal on the cavity and the dielectric layer, and performing pattern manufacturing and etching to form a second circuit layer; forming a first and second solder mask layers correspondingly on the first and second circuit layers, and performing pattern manufacturing on the first solder mask layer or the second solder mask layer to form a bonding pad; and cutting the cavity, the first circuit layer, the second circuit layer, the first solder mask layer and the second solder mask layer.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 12, 2023
    Inventors: Xianming CHEN, Frank BURMEISTER, Lei FENG, Yujun ZHAO, Benxia HUANG, Jinxin YI, Jindong FENG, Yuan LI, Lina JIANG, Edward TENA, Wenshi WANG
  • Publication number: 20230309240
    Abstract: A manufacturing method for a conductive substrate with a filtering function includes preparing a core layer and forming first and second conductive holes in the core layer, forming a sacrificial copper layer on the first conductive hole and on the core layer, forming a metal layer on the second conductive hole, forming a metal post in the first conductive hole, forming a lower insulating layer on the core layer, forming a lower insulative post in the second conductive hole, forming a magnet wrapping around the metal post to obtain a first conductive post, forming an upper insulating layer on the core layer, forming an upper insulative post in the second conductive hole to obtain a second conductive post, removing the upper insulating layer, the lower insulating layer, and the remaining sacrificial copper post layer, followed by flattening.
    Type: Application
    Filed: September 29, 2022
    Publication date: September 28, 2023
    Inventors: Xianming CHEN, Xiaowei XU, Gao HUANG, Benxia HUANG
  • Patent number: 11770859
    Abstract: Provided are an information transmission method, a base station, a terminal and a computer-readable storage medium. The information transmission method includes: a base station sending a first message. The first message includes at least one of: at least one set of channel quality threshold values, where each of the at least one set of channel quality threshold values includes at least one channel quality threshold value; or a deviation value relative to the at least one channel quality threshold value. The at least one channel quality threshold value is set according to at least one following type of channel quality: reference signal receiving power, a reference signal receiving quality, a downlink signal to interference plus noise ratio, a downlink signal to noise ratio, an uplink signal to interference plus noise ratio, an uplink signal to noise ratio, a downlink path loss, or an uplink path loss.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: September 26, 2023
    Assignee: ZTE CORPORATION
    Inventors: Kun Liu, Bo Dai, Huiying Fang, Xianming Chen, Weiwei Yang
  • Patent number: 11769733
    Abstract: A package substrate includes: a glass frame having a through hole and a chip embedding cavity; an electronic component arranged in the chip embedding cavity; a dielectric layer filled on an upper surface of the glass frame and in the chip embedding cavity; a metal pillar passing through the through hole; a circuit layer arranged on the upper surface and/or a lower surface of the glass frame and connected to the electronic component and the metal pillar; and a solder mask arranged on a surface of the circuit layer and having a pad which is connected to the circuit layer.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: September 26, 2023
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Yejie Hong, Benxia Huang, Lei Feng
  • Publication number: 20230282490
    Abstract: A carrier plate for preparing a package substrate according to an embodiment includes a dielectric layer, a seed layer in the dielectric layer, and a copper pillar layer on the seed layer. A bottom end of the seed layer is higher than a lower surface of the dielectric layer. A top end of the copper pillar layer is lower than an upper surface of the dielectric layer. The upper and lower surfaces of the dielectric layer are respectively provided with a first metal layer and a second metal layer.
    Type: Application
    Filed: February 28, 2023
    Publication date: September 7, 2023
    Inventors: Xianming CHEN, Jindong FENG, Benxia HUANG, Gao HUANG, Juchen HUANG
  • Publication number: 20230282565
    Abstract: A packaging structure includes multiple packaging units, and the packaging units include a hard plate region, a winding region, and a fan-out region. In the packaging structure, the hard plate region of the packaging unit is arranged in a stacked manner, some or all of the fan-out regions are packaged with a chip, and some or all of the fan-out regions packaged with a chip are stacked with the hard plate regions after being bent by the winding region. So designed, each fan-out region is individually packaged and then packaged by stacking with each other to achieve the interconnections between a chip and a chip, and between a chip and a substrate without interference between the packaging units.
    Type: Application
    Filed: September 29, 2022
    Publication date: September 7, 2023
    Inventors: Xianming CHEN, Xiaowei XU, Gao HUANG, Benxia HUANG, Wenjian LIN
  • Publication number: 20230276576
    Abstract: A package substrate and a manufacturing method thereof are disclosed. The method includes: providing an inner substrate; processing an adhesive photosensitive material on a surface of a first side of the inner substrate to obtain an adhesive first insulating dielectric layer; mounting a component on the first insulating dielectric layer; and processing a photosensitive packaging material on the first side of the inner substrate to obtain a second insulating dielectric layer, where the second insulating dielectric layer covers the component.
    Type: Application
    Filed: February 25, 2023
    Publication date: August 31, 2023
    Inventors: Xianming CHEN, Wenjian LIN, Gao HUANG, Lei FENG, Jindong FENG, Benxia HUANG, Zhijun ZHANG
  • Publication number: 20230275023
    Abstract: In a method of manufacturing a connector, a first copper pillar layer and a sacrificial copper pillar layer are formed on a temporary bearing plate coated with copper, an etch stop layer is applied on the sacrificial copper pillar layer and electroplated to form a second copper pillar layer, insulating materials is laminated to form a first dielectric layer, a first circuit layer is formed on the first dielectric layer, a second copper pillar layer and a sacrificial copper pillar layer are extended on the first circuit layer, and a sacrificial copper layer is formed on the first circuit layer, insulating material is laminated on the first circuit layer to form a second dielectric layer, the temporary bearing plate is removed, a second and third circuit layers are simultaneously formed on the first and second dielectric layers, and the sacrificial copper layer and the sacrificial copper pillar layer are etched.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Xianming CHEN, Lei FENG, Benxia HUANG, Yejie HONG
  • Patent number: 11743902
    Abstract: Provided are an information transmission method and apparatus, the method includes: receiving, by a terminal, a signal sent by a base station at a preset first time-frequency position; and detecting the signal, and determining whether to detect a physical downlink channel according to a detection result for the signal.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: August 29, 2023
    Assignee: ZTE CORPORATION
    Inventors: Weiwei Yang, Bo Dai, Xianming Chen, Kun Liu, Huiying Fang
  • Patent number: 11722854
    Abstract: Provided are a multicast transmission method and apparatus, and a computer storage medium. The method includes: transmitting multicast channel data according to a multicast search space. The multicast search space is configured for transmitting multicast downlink control information. The multicast channel data includes at least one of multicast control channel data, multicast traffic channel data and multicast control channel change notification data.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: August 8, 2023
    Assignee: ZTE CORPORATION
    Inventors: Xianming Chen, Bo Dai, Jianxun Ai, Kun Liu, Weiwei Yang, Huiying Fang
  • Publication number: 20230232545
    Abstract: A method for manufacturing a packaging substrate, and a packaging substrate are disclosed. The method includes: providing a bottom board with a first circuit layer, the first circuit layer being provided with at least one demand point, and one side of the demand point being provided with a first to-be-avoided region; machining a first intermediate insulating layer on the bottom board, the first intermediate insulating layer including a first intermediate insulating dielectric covering the first to-be-avoided region; machining a first intermediate wiring layer on the first intermediate insulating layer, the first intermediate wiring layer including a first intermediate circuit partially arranged on the first intermediate insulating dielectric and connected to the demand point; machining a first insulating layer on the first intermediate wiring layer which is stacked on the bottom board and covers the first intermediate wiring layer; and machining a circuit build-up layer on the first insulating layer.
    Type: Application
    Filed: December 22, 2022
    Publication date: July 20, 2023
    Inventors: Xianming CHEN, Lei FENG, Benxia HUANG, Wenjian LIN, Gao HUANG
  • Patent number: 11689333
    Abstract: Provided are a signal transmission method and system, which relates to wireless communications. The method includes: transmitting, by a first node, a first signal. The first signal comprises at least one of: at least one first structure, or at least one second structure. The first structure includes at least one symbol group, and the symbol group of the first structure includes a cyclic prefix and at least one symbol or includes a cyclic prefix, at least one symbol and a guard period. Each symbol group of the first structure occupies a same subcarrier or a same frequency resource in a frequency domain. The second structure includes at least one symbol group, and the symbol group of the second structure comprises a cyclic prefix and at least one symbol or includes a cyclic prefix, at least one symbol and a guard period. Each symbol group of the second structure occupies a same subcarrier or a same frequency resource in the frequency domain.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: June 27, 2023
    Assignee: ZTE Corporation
    Inventors: Kun Liu, Bo Dai, Xianming Chen, Weiwei Yang, Huiying Fang
  • Publication number: 20230197739
    Abstract: A capacitor and inductor embedded structure and a manufacturing method therefor, and a substrate are disclosed. The method includes: providing a metal plate; sequentially depositing and etching a first protective layer, a thin film dielectric layer, a second protective layer, and an upper electrode layer on an upper surface of the metal plate to form a thin film capacitor and a capacitor upper electrode; pressing an upper dielectric layer to the upper surface of the metal plate, covering the thin film capacitor and the capacitor upper electrode, and etching the metal plate to form a capacitor lower electrode; pressing a lower dielectric layer to a lower surface of the metal plate, and performing drilling on the upper dielectric layer and the lower dielectric layer to form inductor through holes and capacitor electrode through holes; electroplating metal to form an inductor and circuit layers.
    Type: Application
    Filed: July 24, 2020
    Publication date: June 22, 2023
    Inventors: Xianming CHEN, Lei FENG, Weiyuan YANG, Benxia HUANG, Yejie HONG
  • Publication number: 20230199957
    Abstract: A multilayer substrate and a manufacturing method thereof are disclosed. The multilayer substrate includes two or more dielectric layers laminated in sequence; a public line disposed at a top or bottom dielectric layer of the two or more dielectric layers; and two or more first through hole pillars respectively each embedded in a respective one of the dielectric layers, and the first through hole pillars are connected in cascade and then connected with the public line.
    Type: Application
    Filed: July 24, 2020
    Publication date: June 22, 2023
    Inventors: Xianming CHEN, Lei FENG, Benxia HUANG, Yejie HONG
  • Patent number: 11682621
    Abstract: A connector for implementing multi-faceted interconnection according to an embodiment of the present disclosure includes a first dielectric layer between a first circuit layer and a second circuit layer, a first copper pillar layer connecting the first circuit layer and the second circuit layer in the first dielectric layer, a second dielectric layer on the first circuit layer, a third circuit layer on the second dielectric layer, and a vertical second copper pillar layer connected to the third circuit layer, wherein an opening is formed in the second dielectric layer to expose the first circuit layer, and the second copper pillar layer exposes side faces facing side end faces of the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: June 20, 2023
    Assignee: Zhuhai ACCESS Semiconductor Co., Ltd
    Inventors: Xianming Chen, Lei Feng, Benxia Huang, Yejie Hong
  • Publication number: 20230189444
    Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: June 15, 2023
    Inventors: Xianming CHEN, Lei FENG, Gao HUANG, Benxia HUANG, Yejie HONG
  • Publication number: 20230178298
    Abstract: An embedded inductance structure includes an insulating layer, an inductance located in the insulating layer, a multi-layer conducting circuit located in the insulating layer and on the upper surface and lower surface of the insulating layer, and a multi-layer conductive copper column layer located in the insulating layer. The inductance and the multi-layer conducting circuit are conductively connected via the multi-layer conductive copper column layer, and the inductance includes a magnet and an inductance coil in direct contact with the magnet, and the inductance coil is composed of a multi-layer conductive coil and a conductive copper column located between adjacent conductive coils. The multi-layer conductive coils are respectively in a ring shape with a notch and are disconnected at the notch, and the positions of the conductive copper columns located on the upper side and lower of each conductive coil are different in the longitudinal direction.
    Type: Application
    Filed: September 29, 2022
    Publication date: June 8, 2023
    Inventors: Xianming CHEN, Xiaowei XU, Gao HUANG, Benxia HUANG, Jindong FENG