Abstract: An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array.

Abstract: A method and apparatus are disclosed for detecting a pilot signal in a wireless receiver using coherent combining/noncoherent detection techniques. Coherent combining/noncoherent detection techniques are used to detect the pilot signal whenever the receiver is already frequency locked, or otherwise known to have a small frequency offset. Conventional noncoherent combining/noncoherent detection techniques are utilized to initially acquire the timing of the forward channel. Once the receiver is frequency locked, coherent combining/noncoherent detection techniques may be used to continuously detect the pilot signals. After the receiver is frequency locked, the residue frequency error is small over several consecutive correlator outputs. The correlator outputs can thus be combined coherently (since the frequency error is known to be small), and the phase dependency is then eliminated by noncoherent detection.

Abstract: An iterative decoder decodes a frame of encoded data that includes error detection information, and terminates the iterative decoding based on a comparison of the decoded frame with the error detection information. The iterative decoder may have a maximum number of specified iterations, but may terminate the number of iterations early under specified conditions. The encoded data includes error detection information for parity check calculation. Error detection information may be in accordance with an error detection code, such as a cyclic redundancy check (CRC) code. After each iteration of decoding, a parity check is calculated for the decoded frame. Early termination of decoding may occur prior to an intermediate iteration threshold M of iterations when the parity check value of the decoded frame is equivalent to the parity check value calculated from the error detection information.

Abstract: An N-stage finite impulse response (FIR) filter embodying the invention includes a first filter section whose filter coefficients are made either 1 or zero (rather than 1 and −1) in order to produce a first output (i.e., C1) and a second filter section for producing a second output (i.e., C2), which when combined (added to or subtracted from) with the first output produces an output function (i.e., Cn) which is equal to that produced by an N-stage FIR filter implementing filter coefficients having a value of either 1 or −1.

Abstract: A method and apparatus that utilizes soft outputs from a paging device demodulator to perform frame synchronization is provided. The soft outputs are summed after being correlated to a first pattern associated with a paging protocol. The summation is then compared to a frame synchronization threshold. Frame synchronization occurs when the summation reaches the threshold. Using soft outputs, and a summation of the outputs based on a correlation with the first pattern, the method and apparatus require less processing, are more efficient and are more reliable than conventional synchronization schemes.

Abstract: Inter-frequency handoffs in a CDMA or other wireless communication system are controlled using a noise-limited coverage trigger metric which is able to distinguish between same-frequency cell boundaries and other-frequency cell boundaries in the system. The trigger metric may be generated as a function of an average signal-to-noise measure for pilot signals received at a mobile station of the system and a linear sum of the signal-to-noise measures. The signal-to-noise measures may be generated in the mobile station and included in messages transmitted from the mobile station to one or more base stations of the system. The trigger metric is used to control a handoff from a current frequency to a new frequency in an ongoing call. The trigger metric may alternatively be based on a measure of mobile receive power alone.

Abstract: A methods comprising a hybrid early-termination strategy and an output selection procedure for iterative decoders are disclosed. The hybrid early-termination strategy combines the output-comparison-based method with the CRC-check-based method. The hybrid approach is far more superior in termination reliability in either of the two individual approaches, without their disadvantages. The hybrid termination strategy effectively and reliably terminates the iterative decoding process, cutting the majority of the computational load while eliminating the degradation in the bit error rate (BER) and frame-error-rate (FER) performance due to incorrectly terminated frames. The output selection procedure chooses the best possible decoded frame among those from all iterations, eliminating the iteration abnormality that is inherent in the iterative decoding approach, and improving the BER performance of the standard iterative decoders.

Abstract: The present invention discloses a device for generating multiple spreading sequences efficiently. In a preferred embodiment, the eight different spreading sequences are generated in parallel. In this embodiment, the spreading sequence generator comprises a master sequence generator and eight secondary sequence generators. The spreading sequence generator also comprises eight different modulo-2 adders which are used for generating parity check sum outputs. The master sequence generator is responsible for creating a master output from the first subgroup. The secondary sequence generators create eight different secondary outputs. Each of the secondary outputs is combined with the master output through one of the eight modulo-2 adders to create eight different spreading sequences. In an alternative embodiment, the principles of the present invention may be used to generate such spreading sequences in a sequential manner.

Abstract: Inter-frequency handoffs in a CDMA or other wireless communication system are controlled using a noise-limited coverage trigger metric which is able to distinguish between same-frequency cell boundaries and other-frequency cell boundaries in the system. The trigger metric may be generated as a function of an average signal-to-noise measure for pilot signals received at a mobile station of the system and a linear sum of the signal-to-noise measures. The signal-to-noise measures may be generated in the mobile station and included in messages transmitted from the mobile station to one or more base stations of the system. The trigger metric is used to control a handoff from a current frequency to a new frequency in an ongoing call. The trigger metric may alternatively be based on a measure of mobile receive power alone.

Abstract: An apparatus and method for generating a sine wave signal for a desired phase input. The sine wave signal is generated by implementing a linear expansion of the sine function. An incoming phase value is divided into a base phase value and an incremental phase value. The sine value for each base phase value is stored in a look-up table. The sine values for phase values falling between base phase values are generated using a linear expansion of the sine function.

Abstract: A method of extracting an information bearing signal .omega.(n) from a base-band signal in the form of an inverse function with a digital signal processor. The processor includes memory and utilizes a minimum number of instructions stored in the memory. The base-band waveform comprises a plurality of complex-valued samples having respective I and Q components. The method includes the steps of receiving a first sample at an instant n having respective I(n) and Q(n) components and defining an interval for evaluating potential values for the I(n) and Q(n) components. Next, a step of transforming said I(n) and Q(n) components is performed to have respective threshold values residing in the predefined interval. Then, a step of estimating the transformed components with a series of non-inverted polynomial functions is carried out over the predefined interval.

Abstract: A convolutional encoding apparatus and method for encoding input data with bits stored in a shift register. A predetermined set of coefficient values is provided to define a coefficient mask value. It is then determined whether the bit of the input data is one of a logical zero and a logical one. Only if the bit of the input data is a logical one, the coefficient mask value and the shift register value are combined to produce a next shift register value. Predetermined ones of the bits of the next shift register value are then selected as coded output data.

Abstract: An artificial neural network (ANN) decoding system decodes a convolutionally-encoded data stream at high speed and with high efficiency. The ANN decoding system implements the Viterbi algorithm and is significantly faster than comparable digital-only designs due to its fully parallel architecture. Several modifications to the fully analog system are described, including an analog/digital hybrid design that results in an extremely fast and efficient Viterbi decoding system. A complexity and analysis shows that the modified ANN decoding system is much simpler and easier to implement than its fully digital counterpart. The structure of the ANN decoding system of the invention provides a natural fit for VLSI implementation. Simulation results show that the performance of the ANN decoding system exactly matches that of an ideal Viterbi decoding system.