Abstract: The invention relates to packaging of a novel ferroelectric polymer memory device. Packaging is configured with a recess geometry into which the ferroelectric polymer memory device extends, that resists contact with the polymer portion of the ferroelectric polymer memory device. In one embodiment, an embedded recess geometry is used that resists thermal and mechanical stresses upon the polymer.

Abstract: The invention relates to discrete, spaced-apart ferroelectric polymer memory device embodiments. The ferroelectric polymer memory device is fabricated by spin-on polymer processing and etching using photolithographic technology. The size of the discrete, spaced-apart ferroelectric polymer structures may be tied to a specific photolithography minimum feature dimension.

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions.

Abstract: An integrated circuit (IC) package process is provided that includes forming a first via hole in a first substrate. Patterning signal lines on a first surface and a second surface of the first substrate. Attaching a second substrate to the first surface of the first substrate. Electronically connecting a portion of the signal lines of the first substrate and the second substrate. Attaching an electrical element to the first surface of the first substrate. Forming a via hole in a third substrate. Introducing conductive material over a first surface and a second surface of the third substrate. Forming a second circuit pattern on the first surface and the second surface of the third substrate. Additionally, attaching the third substrate to the first substrate with a second layer of adhesive. In an alternative embodiment, a process includes forming a via hole in a first substrate.

Abstract: Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A microelectronic package including a microelectronic die having an active surface and at least one side. An encapsulation material is disposed adjacent the microelectronic die side(s). A portion of the encapsulation material is removed to expose a back surface of the microelectronic die which has a metallization layer disposed thereon. A protective layer is disposed on the metallization layer prior to encapsulation, such that when the portion of the encapsulation material is removed, the protective layer prevents the metallization layer from being damaged. After the portion of the encapsulation material is removed, the protective layer is removed and the metallization layer is exposed. A heat spreader may then be attached to the microelectronic die by abutting the heat spreader against the metallization layer and reflowing the metallization layer.

Abstract: A method is provided including attaching an encapsulant to an integrated circuit (IC), forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, attaching a first surface of the substrate to the encapsulant so that the substrate is connected to the IC, attaching an electrical element to a second surface of the substrate, and electronically connecting the first surface of the substrate and the second surface of the substrate.

Abstract: A microelectronic package fabrication technology that attaches at least one microelectronic die onto a heat spreader and encapsulates the microelectronic die/dice thereon which may further include a microelectronic packaging core abutting the heat spreader wherein the microelectronic die/dice reside within at least one opening in a microelectronic package core. After encapsulation, build-up layers may be fabricated to form electrical connections with the microelectronic die/dice.

Abstract: According to an embodiment of the invention, an integrated circuit (IC) package is provided that includes a flexible circuit board that has a first surface and a second surface. An integrated circuit mounted to the first surface of the flexible circuit board is provided. An electrical element is attached to the second surface of the flexible circuit board. Also, an encapsulant is attached to the flexible circuit board and the integrated circuit. The flexible circuit board includes at least one layer of dielectric that is no greater than approximately 35 microns thick. In another embodiment, the integrated circuit and the electrical element may be interchanged. A method is provided including attaching an encapsulant to an IC, forming a substrate from at least one layer of dielectric, attaching at least one electrical contact to the substrate, and attaching the substrate to the encapsulant so that the substrate is connected to the IC.

Abstract: Methods and apparatuses are disclosed in which a refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

Abstract: One embodiment of the invention involves a refractory layer formed over a substrate during rapid thermal processing in which ambient hydrogen is used in a thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350° C. to approximately 550° C.

Abstract: A method for forming a material in an opening on a substrate, such as a wafer, using an electron cyclotron resonance-assisted high density plasma physical vapor deposition system. The method comprises the steps of: maintaining a pressure in the range of approximately 1 mTorr to approximately 6 mTorr; generating a plasma by providing a microwave power in the range of approximately 3 kilowatts (kW) to approximately 5 kW; applying a direct current (DC) voltage to a target source of the material in the range of approximately (negative) -600 volts to approximately -1000 volts; providing a current of a predetermined amount to a first electromagnet; and providing a current to a second electromagnet that is less than said predetermined amount, wherein said second electromagnet is disposed below said first electromagnet; and forming a layer of the material in the opening.

Abstract: A device and methods of forming an interconnection within a prepatterned channel in a semiconductor device are described. The present invention includes a method of forming an interconnect channel within a semiconductor device. A first dielectric layer is deposited over a substrate and patterned to form a contact opening that is subsequently filled with a contact plug. A second dielectric layer is deposited over the patterned first dielectric layer and the contact plug. The second dielectric layer is patterned to form the interconnect channel, wherein the first dielectric layer acts as an etch stop to prevent etching of the substrate. The present invention also includes a method of forming an interconnect. A dielectric layer is deposited over a substrate and patterned to form an interconnect chapel. A metal layer is deposited over the patterned dielectric layer and within the interconnect channel.

Abstract: The present invention discloses a method for anisotropically etching metal interconnects in the fabrication of semiconductor devices, especially ULSI interconnects having high aspect ratios. A metal film is first deposited on the appropriate layer of a semiconductor substrate by techniques well-known in the art. A mask layer is deposited over the metal film with openings defined in the mask layer for patterning of the metal film. Ions are then introduced into an exposed region of the metal film to anisotropically form a converted layer of the metal film comprising compounds of the metal. The introduction of the ions into the metal film can be performed by conventional methods, such as through the use of a reactive ion etch system or an ion implantation system, or by any other method which anisotropically forms the metal compounds. The mask layer is then removed by conventional means to leave behind the metal film having a converted layer of metal compounds.

Abstract: An intelligent security device (10) is disclosed for protecting computer software from unauthorized use. The security device (10) is a hardware device having within a microprocessor (36) for interacting with a host computer (32) such that protected software may not be operated unless the security device (10) is in place. Physical duplication of the security device (10) will not result in a workable copy, due to the nature of the microprocessor (36), which is such that information is encoded therein and further such that encryption codes are also stored therein and cannot be discovered after the microprocessor (36) is locked by any known means. A system clock (21) within the microprocessor (36) is adaptable to the purpose of permitting use of the protected software only within limited time parameters.

Abstract: An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

Abstract: An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.

Abstract: An etchback process for etching a refractory metal layer formed on a semiconductor substrate with a greatly reduced micro-loading effect. The etch proceeds in three steps. The first step is a uniform etch which utilizes a gas chemistry of SF.sub.6, O.sub.2 and He and proceeds for a predetermined time to remove most of the metal layer. The second step is a very uniform etch which utilizes a gas chemistry of SF.sub.6, Cl.sub.2 and He and proceeds until the endpoint is detected. The endpoint is detected by measurement and integration of the 772 nm and 775 nm lines of Cl. The third step is a timed etch utilizing a gas chemistry of Cl.sub.2 and He which is used as both an overetch to ensure complete removal of the refractory metal film and as a selective etchant to remove an adhesion underlayer.