Abstract: A system and method for performing low-power analog-to-digital conversion in digital imaging system utilizing a time-indexed multiple sampling technique is presented. The analog-to-digital converter is switched off when the digital image signal resulting from an exposure time selected from a plurality of exposure times satisfies a threshold value.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human epidermal growth factor receptor (EGF-r). Nucelotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly sequences corresponding to contiguous heavy and light chain sequences from CDR1 through CDR3, are provided. Hybridomas expressing such immunoglobulin molecules and monoclonal antibodies are also provided.

Abstract: The presently preferred embodiment of the invention comprises a single ended bit-line from each pixel, small swing bit-line detection, a regenerative sense amplifier, and reference generation using precision analog references.

Abstract: A method of simultaneously providing A/D conversion and multiplication in a Bit-Serial ADCs and single slope ADCs. A bit serial ADC uses a RAMP signal and a BITX signal input to a comparator and 1-bit latch, respectively. When RAMP exceeds an analog input value, the comparator triggers the latch to output the value of BITX. The bits are output serially. The RAMP signal has a staircase shape with voltage levels and voltage steps. In the present invention, multiplication by two coefficients is possible. One coefficient is determined by properly designing RAMP, and the other coefficient is determined by properly designing BITX. Multiplication via RAMP is accomplished by changing the voltage levels by a factor of 1/X, where X is the multiplying coefficient (i.e., multiplication by a factor of 0.5 is accomplished by doubling the voltage of the voltage levels). Multiplication via BITX is accomplished by slowing the frequency of BITX by a factor of X.

Abstract: An image sensor includes a sensor or a pixel array, a data memory, and a logic circuit, all fabricated on the same integrated chip. The sensor or pixel array outputs digital signals as pixel data representing an image of a scene. The data memory is coupled to the sensor or pixel array for storing the pixel data. The logic circuit is coupled to the data memory and provides a memory interface for exporting the pixel data. The memory interface can be one of a SRAM, a DRAM or a packet protocol synchronous DRAM interface. Including a memory interface in the image sensor allows the image sensor to be coupled directly to the memory interface port of an external image processing unit. The image processing unit can access the image sensor using conventional memory access protocols, thus improving the efficiency and reducing the operational complexity of the image processing unit.

Abstract: An architecture for a digital pixel sensor is disclosed in which the dynamic range of the sensor is increased by taking samples of a subject to be recorded, where each sample is taken over an interval of a different duration than the other samples. In the preferred embodiment of the invention, an array of pixel elements is fabricated in an integrated circuit that also includes a memory space for storing selectively digital signals of the samples from the digital elements.

Abstract: An image sensor architecture that accommodates the relative mismatch of bus width between the image sensor, processor, and memory is disclosed. The preferred embodiment of the invention provides a dual-ported memory structure having a relatively wide data port for receiving data from the image sensor and having a relatively narrow data port for communicating data to and from the processor. In one embodiment of the invention, the memory is organized into banks of a specific width. The banks may be accessed sequentially by the processor, such that the bus width is equivalent to the bank width, and the banks may be accessed simultaneously, such that the bus width is equivalent to the combined bank widths. A simple switching means, operating under processor control, reconfigures the memory on the fly.

Abstract: A circuit includes an analog-to-digital (A/D) converter for multiplexing between a number of analog input signals and converting the selected analog input signals to a digital code representation. The A/D converter includes a comparator having a first input terminal connected to receive the first signal having a number of levels, a second input terminal connected to receive a multiple number of analog input signals, and a third input terminal for receiving a multiple number of input select signals. The comparator includes a multiplexer coupling the multiple number of analog input signals to a multiple number of corresponding input signal paths. The multiplexer selects one of the multiple number of input signal paths based on the multiple number of input select signals. In one embodiment, the A/D converter is applied in a digital image sensor for performing pixel-level analog-to-digital conversion using a multi-channel bit serial ADC technique.

Abstract: An improved technique for updating a memory in digital pixel sensors in which a memory update may be directed to only some of the locations or cells in the memory is disclosed. According to one embodiment, a multiplex scheme is employed, in which a threshold memory identifies the locations within a row of memory that are to be updated. Data are first read out of a row of memory to be updated. The data are copied to a first buffer or other short term storage area within the digital pixel sensor. New data from the sensor portion of the digital pixel sensor to be written to the memory are stored in a second buffer. The contents of the threshold memory are then applied to a select input of a multiplexer, where the contents of the first and second buffers comprise first and second data inputs to the multiplexer. Thus, the output of the multiplexer comprises an updated row of memory in which only those locations that are to be updated have been changed.

Abstract: In accordance with the present invention, there are provided fully human monoclonal antibodies against human epidermal growth factor receptor (EGF-r). Nucelotide sequences encoding and amino acid sequences comprising heavy and light chain immunoglobulin molecules, particularly sequences corresponding to contiguous heavy and light chain sequences from CDR1 through CDR3, are provided. Hybridomas expressing such immunoglobulin molecules and monoclonal antibodies are also provided.