Patents by Inventor Xiao Hong Du
Xiao Hong Du has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11533027Abstract: Data isolators are described. The data isolators include a differential receiver having cross-coupled single-ended amplifiers. The single-ended amplifiers may be referenced to a time-varying reference potential. The cross-coupling of the single-ended amplifiers may provide high speed, low power consumption operation of the data isolator.Type: GrantFiled: October 18, 2019Date of Patent: December 20, 2022Assignee: Analog Devices, Inc.Inventor: Xiao Hong Du
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Publication number: 20210119590Abstract: Data isolators are described. The data isolators include a differential receiver having cross-coupled single-ended amplifiers. The single-ended amplifiers may be referenced to a time-varying reference potential. The cross-coupling of the single-ended amplifiers may provide high speed, low power consumption operation of the data isolator.Type: ApplicationFiled: October 18, 2019Publication date: April 22, 2021Applicant: Analog Devices, Inc.Inventor: Xiao Hong Du
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Patent number: 9813035Abstract: Systems and methods disclosed herein provide for enhancing the low frequency (DC) gain of an operational amplifier with multiple correlated level shifting capacitors. In an embodiment, the operational amplifier is level shifted with a first correlated level shifting capacitor in a first phase and, then, is level shifted again with at least a second correlated level shifting capacitor in at least a second, non-overlapping, consecutive phase. In an embodiment, the multiple correlated level capacitors are controlled by a switching circuit network.Type: GrantFiled: November 2, 2015Date of Patent: November 7, 2017Assignee: Analog Devices, Inc.Inventors: Zhichao Tan, Khiem Quang Nguyen, Xiao Hong Du
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Publication number: 20170126189Abstract: Systems and methods disclosed herein provide for enhancing the low frequency (DC) gain of an operational amplifier with multiple correlated level shifting capacitors. In an embodiment, the operational amplifier is level shifted with a first correlated level shifting capacitor in a first phase and, then, is level shifted again with at least a second correlated level shifting capacitor in at least a second, non-overlapping, consecutive phase. In an embodiment, the multiple correlated level capacitors are controlled by a switching circuit network.Type: ApplicationFiled: November 2, 2015Publication date: May 4, 2017Inventors: Zhichao Tan, Khiem Quang Nguyen, Xiao Hong Du
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Patent number: 7652909Abstract: The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states.Type: GrantFiled: October 21, 2007Date of Patent: January 26, 2010Assignee: Ramtron International CorporationInventor: Xiao Hong Du
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Patent number: 7570090Abstract: A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.Type: GrantFiled: October 30, 2007Date of Patent: August 4, 2009Assignee: Ramtron International CorporationInventor: Xiao Hong Du
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Publication number: 20090108887Abstract: A power-on reset circuit includes a first PNP transistor having an emitter, a base, and a collector coupled to ground; a second PNP transistor having an emitter coupled to the base of the first transistor, and a base and collector coupled to ground; a third PNP transistor having an emitter, a base coupled to the base of the first transistor, and a collector coupled to ground; a first resistor coupled between VDD and an internal node; a second resistor coupled between VDD and the emitter of the first transistor; a third resistor coupled between the internal node and the emitter of the third transistor; and a comparator having a first input coupled to the internal node and a second input coupled to the emitter of the first transistor for generating a power-on reset signal.Type: ApplicationFiled: October 30, 2007Publication date: April 30, 2009Applicant: RAMTRON INTERNATIONAL CORPORATIONInventor: Xiao Hong Du
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Publication number: 20090103348Abstract: The signal margin of a small array 2T/2C memory is increased by writing the ferroelectric load capacitors on the bit lines to complementary states.Type: ApplicationFiled: October 21, 2007Publication date: April 23, 2009Applicant: RAMTRON INTERNATIONAL CORPORATIONInventor: Xiao Hong Du
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Patent number: 7313010Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: June 23, 2006Date of Patent: December 25, 2007Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 7271744Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: December 14, 2006Date of Patent: September 18, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
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Patent number: 7233194Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to its source to turn if off during boostenig. Transistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.Type: GrantFiled: October 9, 2003Date of Patent: June 19, 2007Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus
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Patent number: 7176824Abstract: An encoder utilizes a coding method for use with ferroelectric or other nonvolatile counters which are subject to imprint ensures that all of the bits in the code are frequently switched and not left in a fixed data state. The general coding equation for this method is such that: for an even integer n, it is represented by the conventional binary code of n/2; for an odd integer n, it is represented by the conventional binary code of the one's compliment of (n?1)/2. With this method, every bit switches to its compliment when counting from an even number to an odd number so that imprint is substantially reduced.Type: GrantFiled: November 21, 2003Date of Patent: February 13, 2007Assignee: Ramtron InternationalInventors: Xiao Hong Du, Dennis C. Young
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Patent number: 7142627Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: GrantFiled: March 17, 2005Date of Patent: November 28, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060245286Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: June 23, 2006Publication date: November 2, 2006Inventors: Shan SUN, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 7120220Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: GrantFiled: December 23, 2004Date of Patent: October 10, 2006Assignee: Ramtron International CorporationInventors: Xiao-Hong Du, Craig Taylor
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Patent number: 7116572Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: GrantFiled: November 9, 2004Date of Patent: October 3, 2006Assignee: Ramtron International CorporationInventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Publication number: 20060140331Abstract: A non-volatile counter circuit includes a state machine having a first input for receiving one or more control signals, a second input for receiving a current count value, a third input for receiving historical information, and an output for providing a next count value and an up/down control signal, and a non-volatile counter having an input coupled to the output of the state machine, and an output for providing a non-volatile count value. The non-volatile counter can be implemented onto a single integrated circuit using ferroelectric memory technology. The non-volatile counter circuit includes a first power supply node and a second power supply node for receiving power for operating the non-volatile-counter circuit through a first power supply or a second power supply, or both. The first and second power supplies can be low energy power supplies such as that provided by a sensor, or can be conventional power supplies.Type: ApplicationFiled: December 23, 2004Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060140332Abstract: A counting scheme for a non-volatile counter includes automatic point-of-reference generation implemented in a state machine. Two state variables are used to store the rotation history of the magnet. One variable stores the previous position of the magnet and the other stores the net angle traveled by the magnet from the reference point. The first pulse location after the counter is reset is automatically selected as the reference point until the next counter reset. When the nonvolatile counter counts up or down, i.e. when the magnet travels 360° in either direction, the second state variable is set to zero and the first state variable is set to the reference point, indicating the start of a new revolution.Type: ApplicationFiled: March 17, 2005Publication date: June 29, 2006Inventors: Xiao-Hong Du, Craig Taylor
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Publication number: 20060098470Abstract: A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.Type: ApplicationFiled: November 9, 2004Publication date: May 11, 2006Inventors: Shan Sun, Xiao-Hong Du, Fan Chu, Bob Sommervold
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Patent number: 6909318Abstract: This invention is a new CMOS voltage booster (20) having an output which can be used in memories to boost the word line voltage above VDD or other voltage boosting applications. The CMOS booster includes a NMOS FET (MN1) to charge a boosting capacitor (C1) to VDD at the end of each memory access and includes a PMOS FET (MP1, MP2) to keep the voltage at the output at VDD during standby. By using this combination, the word line rise time, the size of the booster, and the power consumption during access are significantly reduced. The gate of the NMOS FET (MN1) is boosted above VDD+Vthn by a small capacitor (C2) to charge the word line boosting capacitor to VDD at the end of each memory access. The small capacitor (C2) is pre-charged to VDD by a NMOSFET (MN2) whose gate is connected to the word line boosting capacitor. The gate of each PMOS FET (MP1, MP2) is shorted to ists source to turn if off during boostenig. Ttransistor (MP3) facilitates boosting the NMOS FET (MN1) above VDD.Type: GrantFiled: August 27, 2003Date of Patent: June 21, 2005Assignee: Texas Instruments IncorporatedInventors: Xiao Hong Du, Jarrod Eliason, Yunchen Qiu, Bill Kraus