Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: A method and system for providing a magnetic memory are described. The method and system include a plurality of magnetic storage cells, a plurality of bit lines, at least one reference line, and at least one sense amplifier. Each magnetic storage cell includes magnetic element(s) and selection device(s). The magnetic element(s) are programmable using write current(s) driven through the magnetic element. The bit and source lines correspond to the magnetic storage cells. The sense amplifier(s) are coupled with the bit lines and reference line(s), and include logic and a plurality of stages. The stages include first and second stages. The first stage converts at least current signal to at least one differential voltage signal. The second stage amplifies the at least one differential voltage signal. The logic selectively disablies at least one of the first and second stages in the absence of a read operation and enabling the first and second stages during the read operation.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: A method and system for providing a magnetic memory. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: A method and system for providing a magnetic memory is described. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic element(s). Each magnetic element has free and pinned layer(s) and a dominant spacer.

Abstract: A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. The magnetic element is programmed by first and second write currents driven through the magnetic element in first and second directions. The local word lines are connected with the selection device of and have a first resistivity. Each global word line corresponds to a portion of the local word lines and has a resistivity lower than the first resistivity. The bit lines are connected with the magnetic element. The source lines are connected with the selection device. Each source line corresponds to a more than one of the magnetic memory cells and carries the first and second write currents.

Abstract: A method and system for providing and using a magnetic storage cell and magnetic memory is described. The method and system include providing a magnetic element and providing a selection device. The magnetic element is programmable to a first state by a first write current driven through the magnetic element in a first direction and to a second state by a second write current driven through the magnetic element in a second direction. The selection device is connected with the magnetic element. The selection device includes a gate having an aperture therein. The selection device is configured such that the first write current and second write current are provided to the magnetic element across the aperture.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: Optical transmission structures include a waveguide and an optical lens wherein the optical lens has a sufficiently large thickness to allow the formation of a curved front lens surface that collimates transmitted light rays so that they travel within a plane that is coplanar to a working surface. The present invention also relates to a technique for manufacturing the optical transmission structure, which involves the use of a photopolymer material. The optical transmission structure can be implemented in various systems such as a system for optical data input.

Abstract: A delay locked loop based clocking circuit includes a lead delay line followed by a period delay line. The lead delay line receives an input clock signal and includes an analog delay control input. The period delay line has a plurality of taps and an analog delay control input, and is operated such that the N taps divide a single period of an input clock. A selected tap of the period delay line, sometimes called a “virtual zero-degree tap,” is fed back and phase-compared with the input clock signal to adjust the delay of the lead delay line.

Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.

Abstract: A bi-directional global data bus scheme for use in a random access memory which optimizes the performance of the data path for read and write operations while offering a uniform read and write frequency to the external processor or controller is presented. The system makes use of a dual local data bus structure which allows the column address to change on every clock cycle since the two parallel local data paths are activated on alternate clock cycles and therefore operate at half the nominal operating frequency. For the read operation, the global data buses operate differentially at the nominal operating frequency. For the write operation, the global data buses operate at half the nominal operating frequency with each global data bus of a complementary data bus pair being dedicated to either one or the other local data paths for every other clock cycle.