Abstract: An apparatus for training and inferencing a neural network includes circuitry that is configured to generate a first weight having a first format including a first number of bits based at least in part on a second weight having a second format including a second number of bits and a residual having a third format including a third number of bits. The second number of bits and the third number of bits are each less than the first number of bits. The circuitry is further configured to update the second weight based at least in part on the first weight and to update the residual based at least in part on the updated second weight and the first weight. The circuitry is further configured to update the first weight based at least in part on the updated second weight and the updated residual.

Abstract: The present application discloses a display panel including a base substrate; a first micro LED array having a plurality of first micro LED pixels in a matrix along a first direction and a second direction on the base substrate; and a second micro LED array having a plurality of second micro LED pixels on a side of the first micro LED array distal to the base substrate, the plurality of second micro LED pixels being grouped into a plurality of groups of second micro LED pixels successively along the second direction, each of the plurality of groups of second micro LED pixels substantially along the first direction and comprising one or more rows of second micro LED pixels substantially along the first direction. Adjacent groups of the plurality of groups of second micro LED pixels are spaced apart from each other thereby exposing a portion of the first micro LED array.

Abstract: The present disclosure discloses a display device and a manufacturing method thereof. The display device includes a middle frame and an indiscrete flexible display panel bending around the middle frame. The flexible display panel includes a main display panel region on one side of the middle frame, an auxiliary display panel region on another side of the middle frame, and a bending region bending around the middle frame to connect the main display panel region with the auxiliary display panel region.

Abstract: A display assembly includes a display panel and at least one optical film group each disposed on a display surface. Each optical film group includes a quarter-wave plate, a reflective polarizer and an absorbing polarizer. The reflective polarizer includes a reflective portion capable of allowing light with a polarization direction parallel to a polarization axis of the reflective polarizer to pass through and reflecting light with a polarization direction perpendicular to the polarization axis. An orthographic projection of an effective light-emitting area of at least one sub-pixel is substantially within an orthographic projection of the reflective portion. The absorbing polarizer is capable of allowing light with a polarization direction parallel to a polarization axis of the absorbing polarizer to pass through and absorbing light with a polarization direction perpendicular to the polarization axis.

Abstract: The embodiments of the present disclosure disclose an OLED array substrate. The OLED array substrate comprises: a plurality of scan lines; a plurality of data lines; a plurality of OLED pixel units, each OLED pixel unit is connected to a corresponding data line and a corresponding scan line and being connected to a corresponding reset terminal; and a plurality of light detection units, each light detection unit is connected between the reset terminal of one OLED pixel unit and the corresponding data line, is configured to detect a light emitted by a detection light resource to generate a light detection signal, and output the light detection signal via the corresponding data line under a control of a reset signal from the reset terminal.

Abstract: A computer-implemented method for performing an exponential calculation using only two fully-pipelined instructions in a floating point unit that includes. The method includes computing an intermediate value y? by multiplying an input operand with a predetermined constant value. The input operand is received in floating point representation. The method further includes computing an exponential result for the input operand by executing a fused instruction. The fused instructions includes converting the intermediate value y? to an integer representation z represented by v most significant bits (MSB), and w least significant bits (LSB). The fused instruction further includes determining exponent bits of the exponential result based on the v MSB from the integer representation z. The method further includes determining mantissa bits of the exponential result according to a piece-wise linear mapping function using a predetermined number of segments based on the w LSB from the integer representation z.

Abstract: A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) (100) having a processor (105) and a master device (106) having shared access to a single-port memory (104) by activating a timer (102) in a Performance Monitoring Unit (PMU) (101) to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter (103) in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.

Abstract: A synapse network device includes an array of field effect transistor (FET) devices having controllable channel resistance. Pre-neurons are coupled to the array to provide input pulses to the array on first terminals of the FET devices. Post-neurons are coupled to the array to receive outputs from the array on second terminals of the FET devices and provide feedback to the array on third terminals of the FET devices, wherein a state of the FET devices is indicated based upon signals applied to the FET devices.

Abstract: Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

Abstract: The present disclosure provides a display component, a method for manufacturing the same, and a display device. The display component includes a display panel, and a light converging layer and a functional panel sequentially disposed on the display side of the display panel. The display panel includes a plurality of pixels, each pixel includes a plurality of sub-pixels, and the light converging layer includes a plurality of light converging units, one light converging unit is disposed on each of the sub-pixels, the functional panel includes a plurality of functional units. The functional unit may be provided with at least one of a sensor functional unit and a solar energy acquisition unit. A transparent area is provided between every two adjacent functional units, and each transparent area corresponds to each of the plurality of sub-pixels in a one-to-one correspondence.

Abstract: The present disclosure provides a microfluidic chip, a device and a method for chemiluminescence immunoassay. The microfluidic chip includes a base plate, as well as a first liquid inlet channel, a second liquid inlet channel, a third liquid inlet channel, an immune reaction cell, and a luminescent reaction cell formed on a first surface of the base plate. An outlet end of the immune reaction cell is in communication with a liquid inlet end of the luminescent reaction cell, and a primer is disposed in the immune reaction cell for immobilizing an antigen-antibody complex generated in the immune reaction cell.

Abstract: The present disclosure provides an OLED panel comprising: a first substrate; an OLED device on the first substrate; an optical detecting device configured to detect a luminance of the OLED device; and a processor configured to generate a control signal according to brightness information of the OLED device detected by the optical detecting device so as to adjust brightness of the OLED device.

Abstract: This invention relates generally to a system and method of detecting woody breast using image analysis of carcass features, and more particularly to a real-time system and method of detecting woody breast in broilers using non-destructive and/or non-contact image analysis of carcass features. The system and method assess woody breast in broilers at the fillet level using image analysis of the angle or area associated with the tip of the keel bone and surrounding breast meat of broiler carcasses. The method is configured be incorporated into and utilized by vision grading system.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: A reflective liquid crystal display panel includes a first substrate, a second substrate, a first polarizer disposed on a side of the first substrate away from the second substrate, a second polarizer disposed on a side of the second substrate away from the first substrate, liquid crystals, a light guiding plate disposed on a side of the first polarizer away from the first substrate, and a side-entry backlight. The reflective liquid crystal display panel further includes a third polarizer laminated on a side of the light guiding plate away from the first polarizer, a composite layer having a mixture of liquid crystals and dichroic dyes, and a third substrate. The third polarizer has the same polarization direction as the first polarizer and a light absorption axis of the third polarizer is orthogonal to a light absorption axis of the composite layer in a display dark state.

Abstract: The present disclosure provides a display device. The display device includes a display panel; a printed circuit board, which is disposed on a back side of the display panel; a sensor, which is disposed on a side of the printed circuit board close to the display panel; a receiving portion, which is disposed at a position of the display panel corresponding to the sensor, the sensor is embedded into the receiving portion.

Abstract: A method for manufacturing a display screen, including: preparing a first substrate and reserving at least one first hole region on the first substrate; preparing a second substrate and reserving at least one second hole region on the second substrate; adding liquid crystals onto the first substrate or the second substrate and aligning the first substrate with the second substrate such that the first hole region is aligned with the second hole region; and forming a hole penetrating the first substrate and the second substrate through the first hole region and the second hole region. The liquid crystals do not occupy the first hole region and the second hole region.

Abstract: The embodiments of the present disclosure disclose an OLED array substrate. The OLED array substrate comprises: a plurality of scan lines; a plurality of data lines; a plurality of OLED pixel units, each OLED pixel unit is connected to a corresponding data line and a corresponding scan line and being connected to a corresponding reset terminal; and a plurality of light detection units, each light detection unit is connected between the reset terminal of one OLED pixel unit and the corresponding data line, is configured to detect a light emitted by a detection light resource to generate a light detection signal, and output the light detection signal via the corresponding data line under a control of a reset signal from the reset terminal.

Abstract: A circuit is provided. The circuit includes a ferroelectric tunneling junction (“FTJ”) coupled in series with a YR read line. The circuit also includes a pull-up circuit having a write line YW as a first input with an output in series with the FTJ, and a pull-down circuit having the write line YW as a first input with an output in series with the second side of the FTJ.

Abstract: Methods and systems of implementing a convolutional neural network are described. In an example, a structure may receive input signals and distribute the input signals to a plurality of unit cells. The structure may include a plurality of multi-kernel modules that may include a respective set of unit cells. A unit cell may correspond to an element of a kernel being implemented in the convolutional neural network and may include a storage component configured to store a weight of a corresponding element of the kernel. A first pass gate of the unit cell may be activated to pass a stored weight of the unit cell to a plurality of operation circuits in the corresponding unit cell, such that the stored weight may be applied to the input signals. The structure may generate a set of outputs based on the application of the stored weights to the input signals.