Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Abstract: A method for producing recombinant adeno-associated virus, the method including: (1) transforming a gene of interest (GOI) into a recombinant baculovirus, where the recombinant baculovirus has a genome integrated with AAV Rep gene, Cap gene, and rAAV genome ITR-GOI that are needed in the production of the rAAV; and where the ITR-GOI is linked to expression cassette of the Cap gene and the Rep gene by a 5? terminal nucleic acid segment or a 3? terminal nucleic acid segment; (2) infecting host insect larvae with the recombinant baculovirus prepared in (1), such that the rAAV is produced in vivo in the host insect larvae; and (3) lysing the host insect larvae obtained in (2), and extracting and purifying the rAAV.

Abstract: A recombinant baculovirus, including: an adeno-associated virus Rep gene, an adeno-associated virus Cap gene, and an recombinant adeno-associated virus genome ITR-GOI (gene of interest) flanked by rAAV inverted terminal repeats (ITR). The ITR-GOI includes a 5? terminal nucleic acid fragment and a 3? terminal nucleic acid fragment. The ITR-GOI is linked to an expression cassette of the Cap gene and an expression cassette of the Rep gene through the 5? terminal nucleic acid fragment and the 3? terminal nucleic acid fragment, respectively.

Abstract: A method for producing a recombinant adeno-associated virus (rAAV) and a recombinant baculovirus virus, the method including: (1) infecting an insect host packaging cell line with a corresponding recombinant baculovirus integrated with an rAAV genome ITR-GOI (gene of interest flanked by AAV inverted terminal repeats) and an AAV Cap gene or AAV Rep gene; (2) culturing the host packaging cell line infected with the recombinant baculovirus, so as to produce the recombinant adeno-associated virus; and (3) separating and purifying the recombinant adeno-associated virus obtained in (2).

Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

Abstract: A system according to various exemplary embodiments includes a processor and an activity sensor, communication module, digital camera and memory coupled to the processor. The memory stores instructions that, when executed by the processor, causes the system to: generate an image via the digital camera; retrieve activity data associated with a user of the system from the activity sensor; modify the image to represent the activity data within the image; and transmit the modified image, using the communication module, to a server.

Abstract: A method for monolithic integration of a hyperspectral image sensor is provided, which includes: forming a bottom reflecting layer on a surface of the photosensitive region of a CMOS image sensor wafer; forming a transparent cavity layer composed of N step structures on the bottom reflecting layer through area selective atomic layer deposition processes, where N=2m, m?1 and m is a positive integer; and forming a top reflecting layer on the transparent cavity layer. With the method, non-uniformity accumulation due to etching processes in conventional technology is minimized, and the cavity layer can be made of materials which cannot be etched. Mosaic cavity layers having such repeated structures with different heights can be formed by extending one-dimensional ASALD, such as extending in another dimension and forming repeated regions, which can be applied to snapshot hyperspectral image sensors, for example, pixels, and greatly improving performance thereof.

Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract: A method for manufacturing a dummy gate structure. The method may include: forming a dummy gate oxide layer and a dummy gate material layer on a semiconductor substrate sequentially; forming an ONO structure on the dummy gate material layer; forming a top amorphous silicon layer on the ONO structure; forming a patterned photoresist layer on the top amorphous silicon layer; etching the top amorphous silicon layer with the patterned photoresist layer as a mask, the etching being stopped on the ONO structure; etching the ONO structure with the patterned photoresist layer and a remaining portion of the top amorphous silicon layer as a mask, the etching being stopped on the dummy gate material layer; removing the patterned photoresist layer; and etching the dummy gate material layer, the etching being stopped at the dummy gate oxide layer to form a dummy gate structure.

Abstract: A polylactic acid composition is provided having a polymer matrix and a compatibilizer. The polymer matrix includes polylactic acids and acrylonitrile-butadiene-styrene[s]. The compatibilizer is at least one compound selected from the group consisting of: a poly (styrene-ethylene-butadiene-styrene) copolymer grafted with maleic anhydrides, an acrylonitrile-butadiene-styrene copolymer grafted with maleic anhydrides, a polystyrene grafted with maleic anhydrides, and an ethylene-ethyl acrylate-glycidyl methacrylate.

Abstract: The present invention provides a method for manufacturing a gate electrode and a contact wire simultaneously in a gate last process, comprising the steps of: forming a gate trench in an inter layer dielectric layer on a substrate; forming a filling layer in the gate trench and on the inter layer dielectric layer; etching the filling layer and the inter layer dielectric layer to expose the substrate, to thereby form a source/drain contact hole; removing the filling layer to expose the gate trench and the source/drain contact hole; forming metal silicide in the source/drain contact hole; depositing a gate dielectric layer and a metal gate in the gate trench; filling metal in the gate trench and the source/drain contact hole; and planarizing the filled metal. In accordance with the manufacturing method of the present invention, the gate electrode wire will be made of the same metal material as the contact hole such that the two can be manufactured by one CMP process.

Abstract: A polylactic acid composition is provided having a polymer matrix and a compatibilizer. The polymer matrix includes polylactic acids and acrylonitrile-butadiene-styrenes. The compatibilizer is at least one compound selected from the group consisting of: a poly (styrene-ethylene-butadiene-styrene) copolymer grafted with maleic anhydrides, an acrylonitrile-butadiene-styrene copolymer grafted with maleic anhydrides, a polystyrene grafted with maleic anhydrides, and an ethylene-ethyl acrylate-glycidyl methacrylate.

Abstract: The present invention provides a chemical-mechanical planarization method. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP.

Abstract: The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate.