Abstract: In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a clock signal quadrature output frequency and a clock signal in-phase output frequency. The clock generator circuit generates a single clock frequency that is a fraction of the frequency of the clock signal quadrature output frequency and the clock signal in-phase output frequency. The PLL includes a single voltage controlled oscillator (VCO) that generates the single clock frequency. A plurality of dividers is included in the clock generator circuit and is responsive to the clock signal quadrature output frequency and the clock signal in-phase output frequency and generates multiple clock frequencies, each clock frequency being a unique frequency, each of the plurality of dividers generating an output that is phase and frequency synchronized to the single clock frequency.

Abstract: A low-noise amplifier comprises a first amplification circuit that includes a control terminal and a first terminal. An impedance load communicates with the first terminal. A feedback circuit outputs an output current to the first terminal and that generates a bias current, which is output to the control terminal and is based on a difference between the output current and N times a reference current, where N is greater than zero.

Abstract: An analog signal processing circuit comprises a bias circuit, a first circuit including a control input that communicates with the bias circuit, a first terminal that generates an output current, and a second terminal, and a device that communicates with the second terminal of the first circuit, that includes a variable resistor, and that has a resistance that is modulated in response to an input signal to the analog signal processing circuit.

Abstract: A low-noise amplifier with a first amplification circuit that includes a control terminal, a first terminal, and a second terminal that communicates with a first reference voltage. An impedance load that communicates with the first terminal and a feedback circuit that comprises a current source that communicates with a second reference voltage. A comparator circuit that includes a first input, a second input and an output that communicates with the control terminal. A first impedance that communicates with the current source and the first input and that generates a predetermined reference voltage based on a reference current generated by the current source and a second impedance that communicates with the second input and the impedance load wherein the feedback circuit compares a voltage, based on an output current associated with the first terminal, with the reference voltage to generate a bias signal that is applied to the control terminal.

Abstract: A low noise amplifier (LNA) comprises a bias circuit having an output. A first transistor includes a control input that communicates with the bias circuit, a first terminal that generates a LNA output current and a second terminal. A device communicates with the second terminal of the first transistor, includes a variable resistor, and has a resistance that is modulated in response to an input signal to the LNA.

Abstract: A method of amplifying an input signal comprises providing a semiconductor die, forming an LNA input stage having a transconductance, on the semiconductor die, and desensitizing the LNA input stage transconductance to variations in process and environmental conditions.

Abstract: A bias circuit for biasing a linear input stage of an amplifier comprises a first MOS device having a size. A second MOS device has a size and is arranged with the first MOS device in a cascode configuration. The second MOS device is operated in a saturation region. A third MOS device has a size and biases the first MOS device in a triode region. A bias switch ratio of the size of the first MOS device to the size of the third MOS device is greater than one.

Abstract: A low noise amplifier (LNA) comprises an amplifier having an inverting input, a non-inverting input and an output. A first transistor has a control input that communicates with said output of said amplifier, a first terminal that generates a LNA output current and a second terminal that communicates with said inverting input. A device communicates with said second terminal of said first transistor, includes an output and has a resistance that is modulated in response to an input voltage to said LNA. The device is a variable resistor.

Abstract: A dummy circuit is provided to which a bias circuit of a low noise amplifier (LNA) can be coupled to during power down of the LNA. The dummy circuit maintains the bias circuit at an approximately normal operating state to reduce wake up time of the LNA.

Abstract: A low-noise amplifier includes a first amplification device. The first amplification device includes a control terminal, a first terminal, and a second terminal. The low-noise amplifier also includes a feedback circuit in communication with the control terminal and the first terminal. The feedback circuit compares a voltage, corresponding to an output current associated with the first terminal, with a predetermined reference voltage to generate a bias signal applied to the control terminal for biasing the low-noise amplifier.

Abstract: A single-ended-to-differential mixer includes a differential input circuit having a single-ended input. The differential input circuit is responsive to a single-ended input signal to generate first and second signals. The single-ended-to-differential mixer includes a passive tank circuit in communication between a reference voltage and the differential input circuit. The single-ended-to-differential mixer includes a mixer circuit in communication with the differential input circuit and responsive to the first and second signals and a second input signal to generate a differential mixer output signal.

Abstract: A low noise amplifier (LNA) comprises an input stage to amplify an input signal, the input stage having a transconductance that has reduced gain variations in response to changes in process and environmental conditions. The input stage includes a first transistor. A second transistor communicates with the first transistor. A bias circuit biases the first transistor in a triode region and the second transistor in a saturation region, wherein an input of the LNA communicates with a control terminal of the first transistor.

Abstract: A circuit that eliminates an off-chip inductive component connected between an integrated circuit (IC) arranged on a package and an external load comprises a package and an IC that is arranged on the package. A first bondwire arranged on the package has one end that communicates with the external load and an opposite end that communicates with the IC. A second bondwire located on the package has one end that communicates with the external load and an opposite end that communicates with the IC.

Abstract: An electrostatic discharge (ESD) protection circuit is provided for protecting transistors of an integrated circuit (IC) from ESD. The ESD protection circuit includes n transistors with n gates and less than n drains where n is an integer greater than 1. At least m resistors have first ends that communicate with at least one of the transistors of the IC, a blocking capacitor of the IC, an input pad of the IC, and an output pad of the IC, and second ends that connect to corresponding drain terminals of said drains where m is an integer greater than or equal to n/2.

Abstract: An impedance matching circuit is provided for an IC arranged on a package that matches an impedance of an external load. The circuit includes a package, an IC that is arranged on the package, and an impedance matching circuit. The impedance matching circuit includes a first bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with said IC, a capacitance element arranged on the IC, and a second bondwire arranged on the package that has one end that communicates with the external load and an opposite end that communicates with one end of said capacitance element.

Abstract: An LNA comprising an input stage to amplify an input signal. The input stage has a high linear transconductance that has reduced gain variations in response to changes in process and environmental conditions.

Abstract: An input circuit for an integrated circuit (IC), which is mounted on a package having an input pin, rejects signal energy at a first frequency. A first bondwire arranged on the package has one end that communicates with the pin and an opposite end that communicates with components of the IC. A second bondwire located on the package has one end that communicates with the pin and an opposite end that communicates with a capacitance. The capacitance and an inductance of the first and second bondwires resonate at the first frequency to reject signal energy at the first frequency. Bondwires are also used to eliminate external components such as resonant components and impedance matching circuits to reduce cost.

Abstract: An input circuit for an integrated circuit (IC), which is mounted on a package having an input pin, rejects signal energy at a first frequency. A first bondwire arranged on the package has one end that communicates with the pin and an opposite end that communicates with components of the IC. A second bondwire located on the package has one end that communicates with the pin and an opposite end that communicates with a capacitance. The capacitance and an inductance of the first and second bondwires resonate at the first frequency to reject signal energy at the first frequency. Bondwires are also used to eliminate external components such as resonant components and impedance matching circuits to reduce cost.

Abstract: An amplifier comprises a Low Noise Amplifier (LNA) that amplifies a Radio Frequency (RF) signal that includes a transconductance, a gain and an input stage that receives the RF signal. A bias assembly includes a bias circuit with a bias resistance and generates a bias current for the input stage of the LNA, which is related to the bias resistance. A shunt feedback stage amplifies an output of the input stage, generates an RF output and includes a shunt resistance. Changes in the bias resistance due to changes in conditions are substantially offset by changes in the shunt resistance due to the changes in conditions, which reduces variation of the gain of the LNA based on the changes in conditions.

Abstract: An amplifier comprising a Low Noise Amplifier (LNA) to amplify a Radio Frequency (RF) signal. The LNA having a transconductance and including an input stage to receive the RF signal. The LNA again varying as a function of changes in conditions. A bias assembly to generate a bias current to bias the LNA input stage. The bias assembly configured to reduce variation of the LNA gain to changes in conditions.