Abstract: A system having a signal processor for detection of a signal type of a signal has a processor is disclosed. One embodiment is designed to determine a first variable which is characteristic of a first spectrum element of the signal spectrum, and to determine a second variable which is characteristic of a second spectrum element of the signal spectrum, a system for determination of a ratio between the first variable and the second variable, and a detector which is designed to detect the signal type on the basis of the ratio.

Abstract: IR memory for an EGPRS receiver of a mobile station which receives data from a base station, by means of a data transmission channel, whereby the IR memory comprises a first memory region, for the buffering of a Particular number of data blocks with a given first data resolution and a second memory region for the buffering of erroneously-decoded data blocks. The second memory region stores the erroneously-decoded data blocks with a second data resolution which is lower than the first data resolution.

Abstract: In a method for error correcting a data signal that is transmitted via a channel and contains data blocks with associated error checking information, the data signal is first equalized, with calculated soft-bit information. In a subsequent step, the error checking information is evaluated with respect to the data block. If the evaluation of the error checking information shows that a single bit error is present in one message bit, the single bit error is corrected only when a condition that is dependent on the soft-bit information is satisfied.

Abstract: A channel filter (200) with a variable pass bandwidth has a first low-pass filter (200.2) on the input side and is driven by a means (30) for controlling the pass bandwidth as a function of the adjacent channel interference. A first input of the control means (30) is connected to the first low-pass filter (200.2), and a second input is connected to a bandpass filter (200.4) which is connected in parallel with the channel filter (200). The signal path which contains the low-pass filter (200.2) contains a means (37) for removing a DC signal component or DC component.

Abstract: A receiver device includes a first mixer for production of a first analogue intermediate signal by down-mixing of a radio-frequency signal. The device also includes an A/D converter for production of a first digital intermediate signal, a second mixer for production of a second digital intermediate signal from the first digital intermediate signal, and a third mixer for production of a digital baseband signal from the second digital intermediate signal. The second mixer has a higher sampling frequency than the third mixer.

Abstract: A mobile station is disclosed for processing differing radio standards such as GSM/GPRS/EDGE and TD-SCDMA. The mobile station includes a channel decoding unit and a coding unit. The signals of both radio standards are processed both with the coding unit and with the channel decoding unit. The coding unit and the channel decoding unit are arranged in the baseband chip of the mobile station. The TD-SCDMA-specific algorithms can be generated by means of a coprocessor that is electrically connected to the baseband chip or integrated in the baseband chip.

Abstract: A method for equalization of a signal is provided, wherein the equalization is of a signal that is transmitted via a data channel based on the DF method. The method takes account of at least one interference channel, and includes processing of at least two trellis diagrams in each time unit, with the states of at least one of the trellis diagrams describing the data channel. A DF contribution that is used for processing of this trellis diagram includes information about at least one interference channel.

Abstract: In a method for equalization of a signal that is transmitted via a user channel using the DF method, an interference channel is taken into account by the DF contribution that is used for processing of the user channel trellis diagram containing information about the interference channel.

Abstract: In a method to compensate for a step DC disturbance (1) in a baseband signal in a homodyne radio receiver, the time profile of the step DC disturbance within a burst is determined. In order to produce a step-corrected baseband signal, the determined time profile (2) is then calculated from the digitized baseband signal.

Abstract: In a method for error correcting a data signal that is transmitted via a channel and contains data blocks with associated error checking information, the data signal is first equalized, with calculated soft-bit information. In a subsequent step, the error checking information is evaluated with respect to the data block. If the evaluation of the error checking information shows that a single bit error is present in one message bit, the single bit error is corrected only when a condition that is dependent on the soft-bit information is satisfied.

Abstract: An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.

Abstract: An integrated memory is described that has memory blocks with column lines and row lines as well as at least one redundancy row line for replacing in each case one of the row lines in any of the memory blocks. In addition, each memory and memory block has a deactivation unit for deactivating the memory block. The integrated memory has deactivation lines, each of which is connected to an input of the deactivation unit of one of the memory blocks. Each memory block has a deactivation decoder that is connected at the output end to all the deactivation lines. If one of the row lines of a first memory block of the memory blocks is replaced by a redundancy row line of a second memory block of the memory blocks, the deactivation decoder of the second memory block deactivates the first memory block via the corresponding deactivation line.