Patents by Inventor Xiaoguang PEI
Xiaoguang PEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11094738Abstract: The embodiments of the present disclosure provide a photoelectric detector, a method for manufacturing the photoelectric detector, and a detection device. The method for manufacturing the photoelectric detector includes: forming a thin film transistor array layer on a base substrate; forming an organic layer on a side of the thin film transistor array layer facing away from the base substrate; and patterning the organic layer to form a first via hole which enables a signal transmission layer in the thin film transistor array layer to be exposed; and depositing a photoelectric conversion device in the first via hole.Type: GrantFiled: July 10, 2019Date of Patent: August 17, 2021Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haisheng Zhao, Hongxi Xiao, Jiapeng Li, Huigang Jiang, Xiaoguang Pei
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Patent number: 10775668Abstract: Disclosed are a backlight module, a display panel, and a display device. The backlight module includes a module frame and at least one first conductive tip structure disposed inside the module frame, the first conductive tip structure includes a first conductive tip, the first conductive tip being in an exposed state of being exposed out from the module frame. The backlight module, according to a point discharge principle, preferentially performs discharging on static electricity through the conductive tip structure, to provide a novel antistatic backlight module.Type: GrantFiled: January 22, 2017Date of Patent: September 15, 2020Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Zijin Lin, Xiaoguang Pei, Haisheng Zhao, Dongjiang Sun
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Patent number: 10725551Abstract: Embodiments of the present disclosure relate to a three-dimensional touch sensing method, a three-dimensional display device and a wearable device. The three-dimensional touch sensing method, comprising: receiving an electron beam being perpendicularly incident to a preset plane on the preset plane, the electron beam having a preset emission intensity; obtaining a reception position and a reception intensity of the electron beam; determining a projection position of a touch position on the preset plane according to the reception position of the electron beam; and calculating a distance from the touch position to the preset plane according to the reception intensity of the electron beam and the preset emission intensity.Type: GrantFiled: May 10, 2016Date of Patent: July 28, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chong Liu, Wei Wang, Haisheng Zhao, Xiaoguang Pei, Zhilong Peng, Huanping Liu
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Patent number: 10726752Abstract: An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.Type: GrantFiled: June 1, 2017Date of Patent: July 28, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zijin Lin, Haisheng Zhao, Xiaoguang Pei
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Patent number: 10627685Abstract: An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises leading wires, the plurality of leading wires form a plurality of grooves in a fanout area of the array substrate, the plurality of grooves are filled with a filler, and the filler filled in the grooves has an upper surface which is flush with leading wires surrounding the grooves. The filler is made from an insulating and transparent material.Type: GrantFiled: April 25, 2017Date of Patent: April 21, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chong Liu, Haisheng Zhao, Xiaoguang Pei, Zhilian Xiao, Zhilong Peng, Hongxi Xiao, Wei Wang
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Publication number: 20200052031Abstract: The embodiments of the present disclosure provide a photoelectric detector, a method for manufacturing the photoelectric detector, and a detection device. The method for manufacturing the photoelectric detector includes: forming a thin film transistor array layer on a base substrate; forming an organic layer on a side of the thin film transistor array layer facing away from the base substrate; and patterning the organic layer to form a first via hole which enables a signal transmission layer in the thin film transistor array layer to be exposed; and depositing a photoelectric conversion device in the first via hole.Type: ApplicationFiled: July 10, 2019Publication date: February 13, 2020Applicants: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haisheng ZHAO, Hongxi XIAO, Jiapeng LI, Huigang JIANG, Xiaoguang PEI
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Patent number: 10545594Abstract: An array substrate includes a substrate, a first signal line and a second signal line on the substrate, an insulating layer covering the first signal line and the second signal line, and a groove penetrating through the insulating layer. The first signal line and the second signal line are arranged in a same layer and separated from each other. The groove is between the first signal line and the second signal line.Type: GrantFiled: August 15, 2017Date of Patent: January 28, 2020Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chong Liu, Haisheng Zhao, Zhilian Xiao, Hongxi Xiao, Wei Wang, Xiaoguang Pei
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Patent number: 10312270Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.Type: GrantFiled: September 19, 2017Date of Patent: June 4, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zhilian Xiao, Haisheng Zhao, Hongxi Xiao, Xiaoguang Pei, Chong Liu
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Patent number: 10297449Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.Type: GrantFiled: May 9, 2016Date of Patent: May 21, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zijin Lin, Haisheng Zhao, Xiaoguang Pei, Zhilong Peng, Dongjiang Sun
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Publication number: 20190123067Abstract: A method of manufacturing an array substrate assembly and an array substrate assembly manufactured by the method are disclosed. The method includes: manufacturing a gate metal layer on a substrate, the gate metal layer including a gate line and a common electrode signal line spaced from each other; forming a gate insulating layer, an active layer, a source-drain electrode layer, a passivation layer, and a protective pattern on the gate metal layer; and forming, in the passivation layer and the gate insulating layer, a via hole configured for a connection to the common electrode signal line. An orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the via hole on the substrate partly coincide with each other, and the orthogonal projection of the protective pattern on the substrate and an orthogonal projection of the gate line on the substrate partly coincide with each other.Type: ApplicationFiled: September 19, 2017Publication date: April 25, 2019Inventors: Zhilian Xiao, Haisheng Zhao, Hongxi Xiao, Xiaoguang Pei, Chong Liu
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Publication number: 20190096299Abstract: An array substrate is disclosed, which includes a substrate, at least one test line, an insulating layer, and an electrostatic shielding pattern. The at least one test line is disposed over the substrate. The insulating layer is disposed over the at least one test line. The electrostatic shielding pattern is disposed over, and insulated by the insulating layer from, the at least one test line in the array substrate. The electrostatic shielding pattern is configured to absorb, and guide out from the array substrate, static electricity to thereby avoid the static electricity from entering an interior of the array substrate via the at least one test line. A method for manufacturing the array substrate, and a display panel containing the array substrate are also provided in the disclosure.Type: ApplicationFiled: June 1, 2017Publication date: March 28, 2019Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zijin LIN, Haisheng ZHAO, Xiaoguang PEI
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Patent number: 10215628Abstract: The present disclosure relates to an image calibrating method and device of a testing apparatus for thin film transistor (TFT) substrate. The method comprises following steps of: calculating an image offset value by using coordinate information of each pixel in a prescribed target image obtained by the testing apparatus for the thin film transistor substrate; and determining whether the offset value is smaller than a prescribed threshold value, in a case where the offset value is not smaller than the prescribed threshold value, adjusting the image by using the offset value and recalculating the offset value by using the coordinate information of each pixel in the adjusted image; in a case where the offset value is smaller than the prescribed threshold value, calibrating the image obtained by the testing apparatus for the thin film transistor substrate with the offset value as a calibrating value.Type: GrantFiled: June 30, 2014Date of Patent: February 26, 2019Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zijin Lin, Haisheng Zhao, Xiaoguang Pei, Chaoyang Deng, Haitao Ma
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Publication number: 20190012023Abstract: An array substrate includes a substrate, a first signal line and a second signal line on the substrate, an insulating layer covering the first signal line and the second signal line, and a groove penetrating through the insulating layer. The first signal line and the second signal line are arranged in a same layer and separated from each other. The groove is between the first signal line and the second signal line.Type: ApplicationFiled: August 15, 2017Publication date: January 10, 2019Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chong Liu, Haisheng Zhao, Zhilian Xiao, Hongxi Xiao, Wei Wang, Xiaoguang Pei
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Patent number: 10134778Abstract: A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.Type: GrantFiled: October 31, 2016Date of Patent: November 20, 2018Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Xiaoguang Pei, Chong Liu, Zhilian Xiao, Haisheng Zhao, Zhilong Peng
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Publication number: 20180331131Abstract: A method for manufacturing thin film transistor, a method for manufacturing array substrate, an array substrate and a display device are provided. The method for manufacturing thin film transistor includes forming an intermediate layer on a substrate, patterning the intermediate layer to form an intermediate layer reserved region and an intermediate layer unreserved region, where the intermediate layer unreserved region corresponds to a pattern of a first structure layer, forming, on the substrate with a pattern of the intermediate layer, a material layer from which the first structure layer is formed, and removing the intermediate layer, and forming the pattern of the first structure layer through a portion of the material layer remaining on the substrate.Type: ApplicationFiled: May 9, 2016Publication date: November 15, 2018Applicants: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Zijin LIN, Haisheng ZHAO, Xiaoguang PEI, Zhilong PENG, Dongjiang SUN
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Patent number: 10062342Abstract: Embodiments of the present invention provide a LCD Q-Panel, a LCD panel and a LCD apparatus, for solving the technical problem that there is a large loss of a signal over the resistance of the signal transmission line when the signal is loaded into a general signal connection port of the LCD Q-Panel in the prior art. The LCD Q-Panel provided in embodiments of the present invention comprises: a general signal connection port, at least one LCD panel comprising a signal connection point, and at least one voltage follower; the signal input from the general signal connection port is transmitted via the at least one voltage follower to the signal connection point connected to an output terminal of the at least one voltage follower and the LCD panel comprising the signal connection point.Type: GrantFiled: July 23, 2013Date of Patent: August 28, 2018Assignee: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Xiaoguang Pei, Haisheng Zhao, Haitao Ma, Yu Cao
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Publication number: 20180188573Abstract: An array substrate, a method for fabricating the same, a display panel and a display device are disclosed. The array substrate comprises leading wires, the plurality of leading wires form a plurality of grooves in a fanout area of the array substrate, the plurality of grooves are filled with a filler, and the filler filled in the grooves has an upper surface which is flush with leading wires surrounding the grooves. The filler is made from an insulating and transparent material.Type: ApplicationFiled: April 25, 2017Publication date: July 5, 2018Inventors: Chong LIU, Haisheng ZHAO, Xiaoguang PEI, Zhilian XIAO, Zhilong PENG, Hongxi XIAO, Wei WANG
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Publication number: 20180164641Abstract: Disclosed are a backlight module, a display panel, and a display device. The backlight module includes a module frame and at least one first conductive tip structure disposed inside the module frame, the first conductive tip structure includes a first conductive tip, the first conductive tip being in an exposed state of being exposed out from the module frame. The backlight module, according to a point discharge principle, preferentially performs discharging on static electricity through the conductive tip structure, to provide a novel antistatic backlight module.Type: ApplicationFiled: January 22, 2017Publication date: June 14, 2018Applicants: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Zijin Lin, Xiaoguang Pei, Haisheng Zhao, Dongjiang Sun
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Publication number: 20170373095Abstract: A method for manufacturing an array substrate, including: forming a plurality of first metal layer patterns on a base substrate which are independent from each other, each of the plurality of first metal layer patterns including an end at a non-display region of the array substrate; forming an insulating layer on the plurality of first metal layer patterns; and forming a semiconductor pattern on the insulating layer, a portion of semiconductor pattern is disposed directly opposite to the end of the first metal layer patterns.Type: ApplicationFiled: October 31, 2016Publication date: December 28, 2017Applicants: BOE technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Xiaoguang Pei, Chong Liu, Zhilian Xiao, Haisheng Zhao, Zhilong Peng
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Publication number: 20170294465Abstract: A film patterning method is provided. The method comprises: performing a dry etching process on a film to be patterned, so as to form a patterned film; removing a suspended particle on the patterned film; and performing another dry etching process on the patterned film after the suspended particle is removed, to form a final pattern of the film. By moving or completely removing the suspended particle on the patterned film and then performing another dry etching process on the patterned film to etch away the etching residue, existence of the etching residue is completely avoided in the final pattern of the film, so that the product yield is improved and the product quality is ensured.Type: ApplicationFiled: July 28, 2016Publication date: October 12, 2017Applicants: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.Inventors: Xiaoguang Pei, Haisheng Zhao, Zhilong Peng, Hongxi Xiao, Chong Liu, Zhilian Xiao, Zijin Lin, Yunfei Bai, Huigang Jiang, Yiping Dong, Hao Chen, Miao Qiu, Kuo Chang