Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: Techniques for sensing the resistance of a load. In an aspect, a sense resistor is provided in series with the load. Each terminal of the sense resistor is alternately coupled via switches to a sense amplifier. A second input of the sense resistor is coupled to a terminal of the load. The voltage drop across the load and the voltage drop across the load plus sense resistor are alternatively measured. These voltage drops may be digitized and used to compute a resistance of the load using, e.g., a digital processor.

Abstract: Exemplary embodiments are directed to devices and method for operating a charge pump. A method may include activating a first switch coupled between a capacitor and a ground voltage over a first period of a charging phase. The first period may coincide with a non-overlapping time between the charging phase and an output phase. The method may also include activating a second switch coupled between the capacitor and an input voltage over a second period of the charging phase, wherein the first period begins prior to the second period. Further, the method may include deactivating the second switch over a third period of the charging phase and deactivating the first switch over a fourth period of the charging phase, wherein the third period begins prior to the fourth period.

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract: An apparatus for sharing a serial communication port between a plurality of communication channels is described. The apparatus comprises a transceiver that manages communications over the serial communication port. The apparatus also includes a multiplexer coupled to the transceiver, wherein the multiplexer multiplexes the plurality of communication channels. The apparatus also includes identification information circuitry coupled to the multiplexer, wherein the identification information circuitry adds identification information to data from the plurality of communication channels that enables the plurality of communication channels to share the serial communication port. The serial communications port and the multiplexer permit communication between integrated circuits that meet at least one latency metric for the plurality of communication channels when the plurality of communication channels are active.

Abstract: Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).

Abstract: A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.

Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

Abstract: A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.

Abstract: An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations.

Abstract: Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

Abstract: Techniques for reducing surge current in charge pumps. In an exemplary embodiment, one or more switches coupling a terminal of a flying capacitor to a voltage supply are configured to have variable on-resistance. When the charge pump is configured to switch a gain mode from a lower gain to a higher gain, the one or more variable resistance switches are configured to have a decreasing resistance profile over time. In this manner, surge current drawn from the voltage supply at the outset of the gain switch may be limited, while the on-resistance during steady-state charging and discharging may be kept low. Similar techniques are provided to decrease the surge current from a bypass switch coupling the supply voltage to a positive output voltage of the charge pump.

Abstract: An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations.

Abstract: A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.

Abstract: A high voltage tolerant differential receiver circuit includes a voltage divider ladder that is operative to divide in half differential input signals that are greater than threshold voltages of the voltage divider ladder. A pass gate circuit is operative to receive differential input signals that are below the threshold voltage of the voltage divider ladder. Outputs from the voltage divider ladder and the pass gate circuit are provided to separate comparators. Output from the comparators are combined to generate a signal in the voltage domain of receiver circuitry.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. A non-overlapping clock generation circuit comprises a delay lock loop (DLL) circuit that generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. The clock generator circuit may also include voltage-controlled delay cells that generate sets of clock signals delayed from one another by a non-overlapping time (tnlp).

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.