Abstract: Techniques to effectively handle large voltage-controlled oscillator (VCO) gain are described. The techniques utilize (1) a slow high-gain path to provide an average control current that adjusts the center frequency of a VCO and (2) a fast low-gain path to provide an instantaneous control current that adjusts the VCO frequency during normal operation. In one design, the VCO includes a voltage-to-current converter, a current amplifier, a summer, and a current-controlled oscillator (ICO). The voltage-to-current converter receives a control voltage and generates a first current and a second current. The current amplifier amplifies and filters the first current and generates a third current. The summer sums the second current and the third current and generates a control current. The ICO receives the control current and generates an oscillator signal having a frequency determined by the control current.

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.

Abstract: A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.

Abstract: A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

Abstract: A Delay-Locked Loop (DLL) uses a delay line to delay a first signal by a “delay time”, thereby generating a second signal. A capacitor is charged at a first rate starting at a first edge of first signal and continuing until an edge of the second signal. The capacitor is then discharged at a second rate until another edge of the first signal. A control loop controls the delay time such that the amount the capacitor is charged is the same as the amount the capacitor is discharged. The delay time is constant and is substantially independent of variations in the duty cycle of the first signal. In one example, duty cycle distortion cancellation is accomplished by changing the first rate proportionally with respect to changes in first signal duty cycle. In another example, the first and second rates are independent of the duty cycle of the first signal.

Abstract: All-digital techniques for generating periodic digital signals having selectable duty cycles. In one aspect, a computation block is provided for computing the product of a selected duty cycle and a discrete ratio between a reference clock period and a high-frequency oscillator period. The computation block may be coupled to a pulse width generator for generating signals having pulse widths that are integer multiples of the high-frequency oscillator period. In another aspect, a pulse width generator may also accommodate mixed fractional multiples of high-frequency oscillator periods by tapping the individual inverter stages of a delay line matched to the individual inverter stages of a ring oscillator exemplary embodiment of the high-frequency oscillator.

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.

Abstract: The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. In another example, the present patent application comprises a method for converting digital code to an analog signal, comprising charging a reservoir capacitor to a reference voltage level, transferring stored charge from the reservoir capacitor to DAC feedback capacitors, and transferring the stored charge from the DAC feedback capacitors to DAC output terminals.

Abstract: Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ?? ADC) are described. In one design, a ?? ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ?? ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled.

Abstract: Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ?? ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.

Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.

Abstract: Techniques for adaptively generating bias current for a switched-capacitor circuit are described. The switched-capacitor circuit charges and discharges at least one switching capacitor at a sampling rate and may be a ?? ADC that digitizes an analog signal at the sampling rate and provides digital samples. The switched-capacitor circuit may support multiple modes associated with different sampling rates. A bias circuit generates a bias current for the switched-capacitor circuit to be proportional to the sampling rate for a selected mode, to provide a bandwidth proportional to the sampling rate for an operational transconductance amplifier (OTA) within the switched-capacitor circuit, and to track changes in the switching capacitor(s) due to variations in integrated circuit (IC) process and temperature. The settling time of the switched-capacitor circuit may track with the multiple modes and across IC process and temperature variations.

Abstract: A line driver circuit with an output impedance that is set to a value which is based at least in part on the impedance of one or more current sources of the driver circuit. The current source impedance varies depending on the desired output amplitude of the driver circuit. Once the current source impedance is determined, a resistor is selected to be placed in parallel connection with the current source so that the combination of the resistor and the current source impedance will produce a desired output impedance for the driver circuit. Preferably, the driver circuit includes a second current source and second resistor in parallel with each other and a source termination resistor, such that the combination of the current source impedance values and the resistor values produces a desired output impedance for the driver circuit.

Abstract: A dual-path current amplifier having a slow high-gain path and a fast low-gain path is described. In one design, the slow high-gain path is implemented with a positive feedback loop and has a gain of greater than one and a bandwidth determined by a pole. The fast low-gain path has unity gain and wide bandwidth. The two signal paths receive an input current and provide first and seconds currents. A summer sums the first and second currents and provides an output current for the dual-path current amplifier. The dual-path current amplifier may be implemented with first and second current mirrors. The first current mirror may implement the fast low-gain path. The first and second current mirrors may be coupled together and implement the slow high-gain path. The first current mirror may be implemented with P-FETs. The second current mirror may be implemented with N-FETs, an operational amplifier, and a capacitor.

Abstract: Techniques for enhancing the slew rate of an active circuit within a feedback circuit (such as a ?? ADC) are described. In one design, a ?? ADC includes an integrator, a slew rate enhancement circuit, and a control circuit. The integrator receives an input signal and provides an output signal. The slew rate enhancement circuit enhances the slew rate of the integrator based on a feedback signal in the ?? ADC. The slew rate enhancement circuit may provide (i) a boost current for only certain values (e.g., the largest and smallest values) of the feedback signal or (ii) different amounts of boost current for different values of the feedback signal. In one design, the slew rate enhancement circuit includes at least one boost circuit coupled to the integrator. Each boost circuit provides a boost current to enhance the slew rate of the integrator when that boost circuit is enabled.

Abstract: The present patent application comprises a digital to analog converter reference circuit, comprising a capacitor connected to a current source, a positive terminal of the capacitor connected to a first switch, the first switch electrically connecting the positive terminal of the capacitor to a positive input terminal of a DAC circuit, a negative terminal of the capacitor connected to a second switch, the second switch electrically connecting the negative terminal of the capacitor to a negative input terminal of the DAC circuit. In another example, the present patent application comprises a method for converting digital code to an analog signal, comprising charging a reservoir capacitor to a reference voltage level, transferring stored charge from the reservoir capacitor to DAC feedback capacitors, and transferring the stored charge from the DAC feedback capacitors to DAC output terminals.

Abstract: Techniques to effectively handle large voltage-controlled oscillator (VCO) gain are described. The techniques utilize (1) a slow high-gain path to provide an average control current that adjusts the center frequency of a VCO and (2) a fast low-gain path to provide an instantaneous control current that adjusts the VCO frequency during normal operation. In one design, the VCO includes a voltage-to-current converter, a current amplifier, a summer, and a current-controlled oscillator (ICO). The voltage-to-current converter receives a control voltage and generates a first current and a second current. The current amplifier amplifies and filters the first current and generates a third current. The summer sums the second current and the third current and generates a control current. The ICO receives the control current and generates an oscillator signal having a frequency determined by the control current.

Abstract: A driver circuit that has a plurality of output elements that are switched on and off in staggered fashion by signals generated by first and second drive chains of a drive chain configuration. The first drive chain comprises “N” delay elements, each of which produces a time delay equal to tDELAY such that the total time delay produced by the first drive chain is equal to (N×tDELAY). The second drive chain comprises N+1 delay elements, “N” of which produce a time delay equal to tDELAY and one of which produces a time delay equal to ½(tDELAY). Therefore, the total time delay produced by the second drive chain is equal to ((N×tDELAY)+(½tDELAY)). The use of the delay element in the second drive that produces the time delay equal to ½(tDELAY) results in smooth transitions in the transition regions where the driver circuit output signal transitions from high to low and from low to high.