Abstract: A circuit includes a voltage generator and a sensing device. The voltage generator includes a first output and a second output. The first output is configured to output a word line voltage, and the second output is configured to output a flag signal indicates a relationship between the word line voltage and a reference signal. The sensing device includes a first input and a third output. The first input is coupled to the second output of the voltage generator, and the third output of the sensing device is configured to output a value corresponding to capacitance change of word line capacitance loading based on the flag signal.

Abstract: A method includes applying a first read voltage to a word line corresponding to a first word line address in a first read request instruction. The method also includes detecting an obtained second read request instruction. The method further includes when the second word line address included in the second read request instruction is the same as the first word line address, applying a second read voltage to the word line corresponding to the first word line address after the end of the application of the first read voltage.

Abstract: Provided are modeling method and device of a floating wind turbine, which relate to the technical field of wind turbine modeling. The modeling method and device of a floating wind turbine can acquire pre-set state variables and input variables of the floating wind turbine, construct a nonlinear model based on the state variables and the input variables, and establish a control-oriented linear parameter varying model corresponding to the nonlinear model according to the nonlinear model, so as to control the floating wind turbine based on the control-oriented linear parameter varying model. The nonlinear model comprises: a drivetrain subsystem model, a tower subsystem model, a floating platform subsystem model, and a mooring subsystem model.

Abstract: In certain aspects, a memory device includes a plurality of memory cells and a peripheral circuit coupled to the plurality of memory cells. The peripheral circuit includes a page buffer, which includes a page buffer circuit and control logic coupled to the page buffer circuit. The page buffer circuit includes a dynamic storage unit and a first non-dynamic storage unit. The control logic is configured to determine whether an information swapping process is performed between the dynamic storage unit and the first non-dynamic storage unit based on a type of an operation to be performed on the page buffer circuit and an information storage manner between the dynamic storage unit and the first non-dynamic storage unit. The control logic is further configured to perform the operation on the page buffer circuit based on the determining whether the information swapping process is performed.

Abstract: A fault-tolerant control method and apparatus of a floating wind turbine are provided. The fault-tolerant control method and apparatus of a floating wind turbine can acquire a low-order nonlinear model of a pre-established floating wind turbine, establish a switching linear model of the floating wind turbine based on the low-order nonlinear model, acquire a modal parameter of the current floating wind turbine, and determine based on the modal parameter a sub-model that the floating wind turbine currently satisfies, so as to establish a switching sliding mode surface and a full-order state observer of the floating wind turbine based on the sub-model and the modal parameter, and further calculate a feedback output of a controller of the floating wind turbine according to the switching sliding mode surface and the full-order state observer.

Abstract: A method for controlling cache programming of a NAND flash memory is disclosed. A programming failure signal is received by a memory controller from the NAND flash memory indicative of failure of the cache programming. After receiving the programming failure signal, a first page buffer release command is sent by the memory controller to the NAND flash memory to release new programming data cached by the NAND flash memory. The cached new programming data is received by the memory controller from the NAND flash memory. After receiving the cached new programming data, a second page buffer release command is sent by the memory controller to the NAND flash memory to release current programming data used for the cache programming. The current programming data is received by the memory controller from the NAND flash memory. The current programming data is reconstructed by the NAND flash memory after releasing the cached new programming data.

Abstract: Provided are control method and device of an energy-storage coordinated floating wind turbine, relating to the technical field of wind turbines. The control method of an energy-storage coordinated floating wind turbine can construct a primary frequency regulation model of a floating wind farm based on a frequency response unit, construct a second frequency regulation model according to an energy storage system, further construct, according to the primary frequency regulation model and the second frequency regulation model, a frequency regulation model of a hybrid power system containing the floating wind farm, the energy storage system, and a pre-set thermal power unit, and design an overall frequency regulation control strategy of the hybrid power system based on the frequency regulation model of the hybrid power system.

Abstract: A memory device includes an array of memory cells in a plurality of memory strings and arranged in a plurality of rows of memory cells. The memory device also includes a plurality of word lines respectively coupled to the plurality of rows of memory cells, and a peripheral circuit coupled to the plurality of word lines and configured to perform a read operation on a selected row of memory cells of the plurality of rows of memory cells. The selected row of memory cells is coupled to a selected word line, wherein the peripheral circuit is configured to apply a word line voltage on each of the plurality of word lines and determine a highest threshold voltage of the plurality of rows of memory cells based on a change of a word line capacitance loading in response to the word line voltage.

Abstract: A memory device includes at least one memory cell array block and a control logic. The memory cell array block includes multiple layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The memory cell array block is divided into at least two memory cell array subblocks, each subblock comprising a number of layers of memory cells and word line layers provided corresponding to individual layers of memory cells. The control logic is coupled to the memory cell array block, and configured to: erase, read or program the memory cell array block using a block mode or a subblock mode, and when the memory cell array block is erased, read, or programmed under the subblock mode, determine, at least based on a state of one of the two memory cell array subblocks, an operation strategy of the other memory cell array subblock.

Abstract: A method and device for realizing beam alignment are disclosed. The method may include: when first signals are received by two analog subarrays having a same polarization using receiving beams with a same beam direction, acquiring the first signals and the phase center difference therebetween; maintaining the beam direction, changing the phase center difference between the two analog sub-arrays for the first time, and acquiring second signals and the first changed phase center difference; maintaining the beam direction, changing the phase center difference for the second time, and acquiring third signals and the second changed phase center difference; and estimating a DOA of a received signal according to the obtained information, and directing the centers of the receiving beams to the estimated DOA.

Abstract: A sample and hold scheme for temperature measurements for non-volatile memory can enable significant reduction in temperature readout latency. In one example thermometer circuits are enabled at a refresh rate to cause the temperature to be sensed and latched at regular intervals. By performing the temperature readings in the background at a refresh rate instead of on-demand, the temperature is available to service commands with almost no latency.

Abstract: Aspects of the disclosure provide an interface between a host and a multi-plane flash memory. For example, the interface can include a first storage unit, a second storage unit and a controller. The first storage unit can be configured to receive and store a first plane pipeline command issued from the host, and output the first plane pipeline command to a first plane of the flash memory. The second storage unit can be configured to receive and store a second plane pipeline command issued from the host, and output the second plane pipeline command to a second plane of the flash memory. The controller can be electrically connected to the first storage unit and the second storage unit, and configured to output the first and second plane pipeline commands to the first and second planes, respectively, when no read process is performed on the first plane and the second plane.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to determine that a block of the blocks is an open block based on an open block information, and in response to the block of the blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: Memory device might include a controller configured to cause the memory device to determine whether the memory device is waiting to initiate a next phase of an access operation, and in response to determining that the memory device is waiting to initiate the next phase, determine whether there is sufficient available current budget to initiate the next phase in a selected operating mode in response to at least the priority token of the memory device, an expected peak current magnitude for the next phase in the selected operating mode, and additional expected peak current magnitudes for other memory devices. In response to determining that there is sufficient available current budget to initiate the next phase in the selected operating mode, the memory device might output the expected peak current magnitude for the next phase in the selected operating mode from the memory device.

Abstract: A method of treating acute kidney injury in a patient is provided, including administering to the patient a 5-HT3-targeting drug, the 5-HT3A-targeting drug, or the pharmaceutically-acceptable salt or solvate of a 5-HT3-targeting drug or a 5-HT3A-targeting drug, in an amount effective to treat acute kidney injury in the patient.

Abstract: Open block-based read offset compensation in read operation of memory device is disclosed. For example, a memory device includes an array of memory cells arranged in a plurality of blocks and a peripheral circuit coupled to the array of memory cells. The peripheral circuit is configured to, in response to a block of the plurality of blocks being an open block, perform a read operation on a memory cell of the array of memory cells in the block using a compensated read voltage. The compensated read voltage has an offset from a default read voltage of the block.

Abstract: A memory device, a memory system, and a method thereof are provided. In the method, an N-th programming pulse is applied to a word line coupled to memory cells of the memory device each with a target programming state being an i-th programming state. A first sub-verification and an M-th second sub-verification are performed on the memory cells to obtain a first sub-result and an M-th second sub-result, respectively. Based on the M-th second sub-result, a subset of the memory cells is determined to be programmed with an (N+1)-th programming pulse. Then, the (N+1)-th programming pulse is applied to the word line. After applying the (N+1)-th programming pulse to the word line, the memory cells are determined to be successfully programmed to the i-th programming state based on the first sub-result indicating that a number of failed bits in the first sub-verification is less than a first preset value.

Abstract: The present invention discloses an intelligent soft measurement method for wind speed in front of a wind turbine. The method includes: first using laser radar data as a data sample, judging delay orders between input and output by using an AIC or BIC criterion, defining a dynamic difference regression vector according to the delay orders, dividing hyperplanes according to a clustering result by using a machine learning algorithm, and performing dynamic differential input/output nonlinear mapping modeling in a global scope and sub-scopes by using an artificial intelligence dynamic regression algorithm, respectively. Empirical mode decomposition and power spectral density analysis are performed on the wind speed in front of a laser radar measuring machine and the wind speed in front of a soft measurement machine, thereby further verifying the estimation performance of intelligent soft measurement for the wind speed in front of a wind turbine.

Abstract: In certain aspects, a memory device includes memory cells coupled to a same word line and bit lines, respectively, and a peripheral circuit coupled to the memory cells through the word line and the bit lines. Each of the memory cells is in one of states. The peripheral circuit is configured to determine a first number of a first set of the memory cells and a second number of a second set of the memory cells. Threshold voltages of the first set of the memory cells are between a first voltage and a second voltage larger than the first voltage. Threshold voltages of the second set of the memory cells are between the second voltage and a third voltage larger than the second voltage. The peripheral circuit is also configured to estimate a valley voltage corresponding to a first state of the states based, at least in part, on a comparison between the first number and the second number.

Abstract: Methods might include determining whether a particular die of a plurality of dies is expected to initiate a next phase of an operation, setting an expected peak current magnitude of the particular die to the present expected peak current magnitude in response to the expected peak current magnitude of the next phase being less than a present expected peak current magnitude, and setting the expected peak current magnitude of the particular die to the expected peak current magnitude of the next phase in response to the expected peak current magnitude of the next phase being greater than the present expected peak current magnitude if a sum of the expected peak current magnitude of the next phase, and expected peak current magnitudes for each die of the plurality of dies other than the particular die, is less than a particular value. Apparatus might be configured to perform similar methods.