Xiaojie Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.
Abstract: Embodiments relate to a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate, and forming an initial stack structure on the substrate, where the initial stack structure includes a first dielectric layer and a target semiconductor layer alternately stacked in sequence along a first direction adjacent to the substrate; forming, in the initial stack structure, a first trench isolation structure, a second trench isolation structure and a third trench isolation structure arranged at intervals along a second direction and extending along a third direction; forming two spaced gate trenches whose bottom surfaces contact an upper surface of the substrate, where a part of the target semiconductor layer positioned in the gate trench is exposed and suspended; and forming gate structures surrounding the target semiconductor layer in the gate trenches.
Abstract: A signal processing method includes: obtaining first indication information, where the first indication information includes a measurement parameter; performing, by a signal forwarding device based on the measurement parameter, signal quality measurement on a received first uplink signal sent by a target user terminal UE; sending a signal quality measurement result to a base station; if obtaining second indication information sent by the base station, receiving a second uplink signal sent by the target UE, and forwarding the second uplink signal to the base station, where the second indication information is sent by the base station to the signal forwarding device, after the base station determines, based on the signal quality measurement result, to determine to allocate the target UE to the signal forwarding device as subordinate UE.
Abstract: The semiconductor structure forming method includes: providing a base, where the base includes a substrate, a plurality of first semiconductor layers and second semiconductor layers; forming a first sidewall and a second sidewall, each including a support layer and an isolation layer formed on a side of the support layer; forming a plurality of recessed portions separated by the first sidewall, the second sidewall, and the second semiconductor layers, where the recessed portions extend in a horizontal direction and are stacked in a vertical direction; forming a first conductive layer and a filling layer in each recessed portion; removing isolation layers located on a side of the first sidewall that is away from the second sidewall and on a side of the second sidewall that is away from the first sidewall; and removing the first conductive layer located at a bottom of each recessed portion.
Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a plurality of word lines extending along a first direction and arranged at intervals along a third direction; a plurality of semiconductor channels extending along a second direction and arranged at intervals along the third direction, wherein the word line surrounds the semiconductor channel along the third direction; a stepped structure including a plurality of steps, wherein the step is in contact with and connected to the word line, a height of a top surface of any one of the steps is different from a height of a top surface of another one of the steps along the third direction, the steps are arranged in an array along the first direction and the second direction; and a plurality of contact structures, wherein the contact structure is in contact with and connected to the step.
Abstract: A method includes: providing a substrate including a first region and a second region; a stacked structure being formed on the substrate, the stacked structure including a first semiconductor layers and a second semiconductor layers stacked alternately in sequence along a direction perpendicular to a plane where the substrate is located; etching the stacked structure, such that the first semiconductor layers and the second semiconductor layers located in the second region respectively form a first sub-part extending in a first direction and a third sub-part extending in the first direction; the first semiconductor layers and the second semiconductor layers remaining in the first region respectively constitute a second sub-part extending in a second direction and a fourth sub-part extending in the second direction; removing the third sub-part; and forming a first dielectric layer at least filling a gap between two adjacent ones of the first sub-parts.
Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a substrate on which a stacked structure is provided, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction; and a plurality of leading wire posts, wherein at least two leading wire posts are respectively in contact with the memory cells of different layers in different memory cell groups.
Abstract: A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.
Abstract: A semiconductor structure manufacturing method includes: providing a substrate and forming a groove in the substrate; forming a barrier layer on a sidewall of the groove; epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and removing a portion of the intermediate structure and a portion of the substrate to form a fin structure.
Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base, and forming active pillars, a bit line, a word line, and memory structures. Forming the memory structures includes: providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate.
Abstract: This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.
Abstract: Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.
Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a first area and a second area; forming a stack structure on the substrate; and forming a plurality of columns of silicon pillar structures and support structures in the stack structure located on the second area, in which the plurality of columns of silicon pillar structures are arranged at intervals in a first direction; each column of silicon pillar structure includes a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate; the plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers; and any adjacent silicon pillars are connected by the support structure.
Abstract: A joint link-level and network-level intelligent system and method for dynamic spectrum anti-jamming are provided. The system includes a link-level anti-jamming subsystem and a network-level anti-jamming subsystem. The link-level anti-jamming subsystem sets a reward value as system transmission throughput in a single decision cycle, and a user makes an intelligent frequency usage decision based on the obtained reward value to skip a frequency band in which jamming exists. The network-level anti-jamming subsystem performs reasonable frequency band allocation and management for lower-level sub-users when link-level anti-jamming fails to further enhance a frequency domain anti-jamming capability of the entire system. The users make intelligent frequency usage decisions through a dynamic spectrum anti-jamming algorithm based on reinforcement learning to effectively avoid external malicious jamming, realize dynamic spectrum access, and enhance a frequency domain anti-jamming capability of the system.
September 2, 2022
Date of Patent:
October 3, 2023
NANJING UNIVERSITY OF AERONAUTICS AND ASTRONAUTICS
Nan Qi, Luliang Jia, Diliao Ye, Qihui Wu, Xiaojie Li, Yijia Liu, Wei Wang
Abstract: The present disclosure describes techniques for social networking based on trading asset items. The techniques comprise sending a request by a first client computing device for connecting with a second client computing device, displaying a first video comprising a first user and a second video comprising a second user on an interface, determining a first body part of the first user based on a selection of a representative of a first asset item associated with the second user, determining a position of rendering an image of the first asset item on the interface, rendering the image of the first asset item and combining the image into the first video for display of an effect of the first asset item being tried on the first body part of the first user, and receiving the first asset item from the second user based on the effect and user input.
Abstract: Embodiments of this application disclose a data storage method. The method includes: A data storage service system including two nodes is deployed on a wheeled mobile device (for example, an intelligent vehicle, an autonomous vehicle, or a connected vehicle). A first node is a primary node, and a second node is a secondary node. A first process and a second process respectively run on the first node and the second node. When the first node receives a data write request, the first node first invokes a first database engine by using the first process to write data to a first storage module on the first node, and then in a blocking mode, the first node enables the second node to invoke a second database engine by using the second process to perform a same data write operation on a second storage module on the second node.
Abstract: Provided are a processing method, a terminal device, and a medium. The method includes the steps described below. Basic information of a target video is determined; attribute information of the target video is determined based on the basic information; in a case where the attribute information indicates that the target video is a video capable of being structured, chapter division is performed on the target video based on the basic information to obtain at least two video clips; and chapter description information of the at least two video clips, a key frame of the at least two video clips and video description information of the target video are determined.
Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.
Abstract: A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.
Abstract: Method for manufacturing a semiconductor device includes: forming a first area and a second area of a peripheral area on a substrate; forming a first lamination structure in the first area, and forming a second lamination structure in an array area and the second area; performing thermal treatment on the substrate so that atoms in a work function layer are diffused into a second dielectric layer, and an interface interaction occurs between the second dielectric layer and a first dielectric layer; removing the first lamination structure to the second dielectric layer, and removing the second lamination structure to the second dielectric layer; forming a fourth barrier layer and a second conductive layer, a content ratio of metallic element to non-metallic element in a first barrier layer being less than a content ratio of metallic element to non-metallic element in a second barrier layer and a third barrier layer.