Abstract: The present disclosure describes techniques for social networking based on collecting asset items. Features may be extracted from an image comprising an object and captured by a camera. The object may be associated with a location. The location may be determined based on information indicating a position where the camera is located. The object may be recognized based at least in part on the features extracted from the image. An asset item may be displayed in response to recognizing the object.

Abstract: Certain aspects of the present disclosure provide techniques for downlink relaying for passive internet of things (PIoT) communication. An example method includes receiving, from a network entity in a wireless network, configuration information for communicating with at least one passive internet of things (PIoT) device and receiving, from the network entity, a PIoT message, the PIoT message including at least a PIoT relay command instructing the UE to communicate with the at least one PIoT device. The method also includes transmitting, based on the PIoT message, one or more signals to the at least one PIoT device in accordance with the configuration information.

Abstract: The present disclosure provides a display method, apparatus, computer device and storage medium, wherein the method comprises: in response to a trigger operation for any of book recommendation topics, acquiring a plurality of topic posts under the book recommendation topic, and target filtering items matching the topic posts; wherein the target filtering items are determined based on book recommendation information of the topic posts and book information recommended in the topic posts; displaying the target filtering items; and in response to one of the target filtering items being selected, displaying topic posts associated with the one of the target filtering items.

Abstract: Embodiments of the present disclosure provide a semiconductor device, comprising a semiconductor layer, extending along the first direction; the semiconductor layer includes a capacitor area facing the capacitor structure, and the capacitor structure includes: a lower electrode layer, the capacitor dielectric layer and the upper electrode layer, sequentially surrounding the sidewalls of the capacitor area extending along the first direction, a part of the lower electrode layer surrounds the sidewalls of the capacitor region, and also surrounds the bottom of the upper electrode layer, the sidewalls extending along the first direction, and the capacitor dielectric layer is located between the upper electrode layer and the lower electrode layer. The disclosed device improves the capacitance of the capacitor structure while improving the integration density of the semiconductor structure.

Abstract: The present disclosure provides a book page display method and apparatus, a computer device, and a storage medium, wherein the method comprises: in response to a trigger operation on a first book, displaying a book page of the first book; displaying, in the book page, a target topic matched with the first book; wherein at least one of the topic information of the target topic or a second book included in the target topic is matched with the first book.

Abstract: Method for manufacturing a semiconductor device includes: forming a first area and a second area of a peripheral area on a substrate; forming a first lamination structure in the first area, and forming a second lamination structure in an array area and the second area; performing thermal treatment on the substrate so that atoms in a work function layer are diffused into a second dielectric layer, and an interface interaction occurs between the second dielectric layer and a first dielectric layer; removing the first lamination structure to the second dielectric layer, and removing the second lamination structure to the second dielectric layer; forming a fourth barrier layer and a second conductive layer, a content ratio of metallic element to non-metallic element in a first barrier layer being less than a content ratio of metallic element to non-metallic element in a second barrier layer and a third barrier layer.

Abstract: A system for multi-channel data acquisition and precision irrigation and fertilizer application control of crops involving the following steps: obtaining a soil moisture content and a plant status parameter for plants within each homogeneous area; calculating a required soil moisture content for plants within the homogeneous area based on a difference between the required soil moisture content for plants within the planting area and the soil moisture content for plants within the homogeneous area; obtaining types and quality of required fertilizers for plants within the homogeneous area based on the plant status parameter for plants within the homogeneous area; blending an irrigation water and fertilizer solution required by plants within the homogeneous area; and irrigating plants within each homogeneous area according to the irrigation water and fertilizer solution required by plants within the homogeneous area.

Abstract: Disclosed is a straw crushing device capable of driving a sharpening structure, relating to the field of straw crushing. The straw crushing device includes a main housing, the main housing is internally provided with a crushing chamber and a suction chamber, a feeding nozzle is installed outside the main housing, and the feeding nozzle communicates with a feeding end of the crushing chamber. A spline transmission shaft is installed inside the main housing, and penetrates through the crushing chamber and the suction chamber. A driving motor is installed outside the main housing, and the driving motor is connected to the spline transmission shaft. A Y-shaped tool rest is installed on the spline transmission shaft, and the Y-shaped tool rest is located in the crushing chamber.

Abstract: A semiconductor structure includes a substrate and a stack structure located on the substrate. The stack structure includes a plurality of memory units arranged at intervals in a first direction. Each memory unit includes a transistor structure. The transistor structure includes an active structure and a gate layer. At least part of the active structure is distributed around a periphery of part of the gate layer, and the projection of the active structure on a top surface of the substrate is in the shape of a U which opens toward a second direction. Both the first direction and the second direction are parallel to the top surface of the substrate, and the first direction intersects with the second direction. A method for forming the semiconductor structure is also provided.

Abstract: A method for forming a semiconductor structure includes: a base is provided, the base including a first area and a second area located outside the first area, the first area including stack structures and first isolation structures arranged alternately in a first direction, each stack structure including first semiconductor layers and second semiconductor layers stacked onto one another alternately in a third direction, the first direction being a direction in a plane where the base is located, the third direction intersecting with the plane where the base is located; the first semiconductor layers located in the first area, and the first isolation structures located in the first area and located in projection areas of the first semiconductor layers in the first direction are successively removed, to form active dummy connection layers extending in the first direction; and gate structures are formed on surfaces of the active dummy connection layers.

Abstract: Embodiments relate to a method for fabricating a semiconductor structure and a semiconductor structure. The method includes: providing a substrate, and forming an initial stack structure on the substrate, where the initial stack structure includes a first dielectric layer and a target semiconductor layer alternately stacked in sequence along a first direction adjacent to the substrate; forming, in the initial stack structure, a first trench isolation structure, a second trench isolation structure and a third trench isolation structure arranged at intervals along a second direction and extending along a third direction; forming two spaced gate trenches whose bottom surfaces contact an upper surface of the substrate, where a part of the target semiconductor layer positioned in the gate trench is exposed and suspended; and forming gate structures surrounding the target semiconductor layer in the gate trenches.

Abstract: A signal processing method includes: obtaining first indication information, where the first indication information includes a measurement parameter; performing, by a signal forwarding device based on the measurement parameter, signal quality measurement on a received first uplink signal sent by a target user terminal UE; sending a signal quality measurement result to a base station; if obtaining second indication information sent by the base station, receiving a second uplink signal sent by the target UE, and forwarding the second uplink signal to the base station, where the second indication information is sent by the base station to the signal forwarding device, after the base station determines, based on the signal quality measurement result, to determine to allocate the target UE to the signal forwarding device as subordinate UE.

Abstract: The semiconductor structure forming method includes: providing a base, where the base includes a substrate, a plurality of first semiconductor layers and second semiconductor layers; forming a first sidewall and a second sidewall, each including a support layer and an isolation layer formed on a side of the support layer; forming a plurality of recessed portions separated by the first sidewall, the second sidewall, and the second semiconductor layers, where the recessed portions extend in a horizontal direction and are stacked in a vertical direction; forming a first conductive layer and a filling layer in each recessed portion; removing isolation layers located on a side of the first sidewall that is away from the second sidewall and on a side of the second sidewall that is away from the first sidewall; and removing the first conductive layer located at a bottom of each recessed portion.

Abstract: A method includes: providing a substrate including a first region and a second region; a stacked structure being formed on the substrate, the stacked structure including a first semiconductor layers and a second semiconductor layers stacked alternately in sequence along a direction perpendicular to a plane where the substrate is located; etching the stacked structure, such that the first semiconductor layers and the second semiconductor layers located in the second region respectively form a first sub-part extending in a first direction and a third sub-part extending in the first direction; the first semiconductor layers and the second semiconductor layers remaining in the first region respectively constitute a second sub-part extending in a second direction and a fourth sub-part extending in the second direction; removing the third sub-part; and forming a first dielectric layer at least filling a gap between two adjacent ones of the first sub-parts.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes: a plurality of word lines extending along a first direction and arranged at intervals along a third direction; a plurality of semiconductor channels extending along a second direction and arranged at intervals along the third direction, wherein the word line surrounds the semiconductor channel along the third direction; a stepped structure including a plurality of steps, wherein the step is in contact with and connected to the word line, a height of a top surface of any one of the steps is different from a height of a top surface of another one of the steps along the third direction, the steps are arranged in an array along the first direction and the second direction; and a plurality of contact structures, wherein the contact structure is in contact with and connected to the step.

Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a substrate on which a stacked structure is provided, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction; and a plurality of leading wire posts, wherein at least two leading wire posts are respectively in contact with the memory cells of different layers in different memory cell groups.

Abstract: A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate and forming a groove in the substrate; forming a barrier layer on a sidewall of the groove; epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and removing a portion of the intermediate structure and a portion of the substrate to form a fin structure.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base, and forming active pillars, a bit line, a word line, and memory structures. Forming the memory structures includes: providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate.

Abstract: Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.