Abstract: A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure comprises a substrate on which a stacked structure is provided, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction; and a plurality of leading wire posts, wherein at least two leading wire posts are respectively in contact with the memory cells of different layers in different memory cell groups.

Abstract: A semiconductor structure comprises a substrate, wherein the substrate is provided with a stacked structure, the stacked structure comprising a plurality of memory cell groups arranged in a first direction, each of the memory cell groups comprising multiple layers of memory cells arranged in a second direction, the stacked structure further comprising a plurality of horizontal signal lines arranged in the second direction, wherein each of the horizontal signal lines is in contact with one layer of the memory cells; and a plurality of leading wire posts arranged in the first direction, wherein the plurality of leading wire posts and the plurality of horizontal signal lines are arranged along a third direction, and the leading wire posts are connected to the horizontal signal lines.

Abstract: A semiconductor structure manufacturing method includes: providing a substrate and forming a groove in the substrate; forming a barrier layer on a sidewall of the groove; epitaxially growing a channel material from a bottom of the groove to form an intermediate structure in the groove; and removing a portion of the intermediate structure and a portion of the substrate to form a fin structure.

Abstract: Embodiments of the present disclosure relate to the field of semiconductors, and provide a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base, and forming active pillars, a bit line, a word line, and memory structures. Forming the memory structures includes: providing an isolation layer between the word line and the memory structures, and forming a first conductive layer, a dielectric film, and a second conductive layer that are continuously and sequentially stacked on a side surface of the isolation layer and a surface of the active pillar; and etching to remove a part of the first conductive layer located on the side surface of the isolation layer, to expose a side surface of the dielectric film, and taking a remaining part of the first conductive layer as the first electrode plate.

Abstract: This invention relates to a semiconductor structure and a method for forming the semiconductor structure. The method for forming a semiconductor structure includes the following steps: forming a stacking layer on a top surface of a substrate, where the stacking layer includes a plurality of semiconductor layers arranged at intervals in a first direction, and the stacking layer includes a transistor region, a capacitor region, and a bit line region, where the semiconductor layers include semiconductor columns arranged at intervals in a third direction; forming, in the capacitor region, a capacitor extending in the second direction; forming a word line in the transistor region, where the word line extends in the third direction and continuously covers the semiconductor columns arranged at intervals in the third direction; and forming a bit line in the bit line region, where the bit line extends in the first direction.

Abstract: Embodiments relates to a semiconductor structure and a formation method thereof. The method for forming a semiconductor structure includes: forming a stacked layer on a top surface of a substrate, where the stacked layer includes a plurality of semiconductor layers spaced along a first direction, the stacked layer includes a transistor region, and a capacitor region and a bit line region; forming a capacitor extending along the second direction in the capacitor region; forming a word line in the transistor region, the word line extending along the first direction; and forming a bit line in the bit line region, the bit line extending along the third direction.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a first area and a second area; forming a stack structure on the substrate; and forming a plurality of columns of silicon pillar structures and support structures in the stack structure located on the second area, in which the plurality of columns of silicon pillar structures are arranged at intervals in a first direction; each column of silicon pillar structure includes a plurality of silicon pillars that are arranged at intervals and are parallel to the substrate; the plurality of silicon pillars in the plurality of columns of silicon pillar structures are distributed in a plurality of layers; and any adjacent silicon pillars are connected by the support structure.

Abstract: A joint link-level and network-level intelligent system and method for dynamic spectrum anti-jamming are provided. The system includes a link-level anti-jamming subsystem and a network-level anti-jamming subsystem. The link-level anti-jamming subsystem sets a reward value as system transmission throughput in a single decision cycle, and a user makes an intelligent frequency usage decision based on the obtained reward value to skip a frequency band in which jamming exists. The network-level anti-jamming subsystem performs reasonable frequency band allocation and management for lower-level sub-users when link-level anti-jamming fails to further enhance a frequency domain anti-jamming capability of the entire system. The users make intelligent frequency usage decisions through a dynamic spectrum anti-jamming algorithm based on reinforcement learning to effectively avoid external malicious jamming, realize dynamic spectrum access, and enhance a frequency domain anti-jamming capability of the system.

Abstract: The present disclosure describes techniques for social networking based on trading asset items. The techniques comprise sending a request by a first client computing device for connecting with a second client computing device, displaying a first video comprising a first user and a second video comprising a second user on an interface, determining a first body part of the first user based on a selection of a representative of a first asset item associated with the second user, determining a position of rendering an image of the first asset item on the interface, rendering the image of the first asset item and combining the image into the first video for display of an effect of the first asset item being tried on the first body part of the first user, and receiving the first asset item from the second user based on the effect and user input.

Abstract: Embodiments of this application disclose a data storage method. The method includes: A data storage service system including two nodes is deployed on a wheeled mobile device (for example, an intelligent vehicle, an autonomous vehicle, or a connected vehicle). A first node is a primary node, and a second node is a secondary node. A first process and a second process respectively run on the first node and the second node. When the first node receives a data write request, the first node first invokes a first database engine by using the first process to write data to a first storage module on the first node, and then in a blocking mode, the first node enables the second node to invoke a second database engine by using the second process to perform a same data write operation on a second storage module on the second node.

Abstract: Provided are a processing method, a terminal device, and a medium. The method includes the steps described below. Basic information of a target video is determined; attribute information of the target video is determined based on the basic information; in a case where the attribute information indicates that the target video is a video capable of being structured, chapter division is performed on the target video based on the basic information to obtain at least two video clips; and chapter description information of the at least two video clips, a key frame of the at least two video clips and video description information of the target video are determined.

Abstract: A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.

Abstract: A semiconductor structure includes a substrate; at least one layer of memory structure formed on the substrate, in which each layer of memory structure comprises a bit line structure and a plurality of capacitor structures symmetrically distributed on both sides of the bit line structure, the plurality of capacitor structures and the bit line structure extend in a first direction parallel to the substrate surface; a plurality of word line structures formed in the at least one layer of memory structure, which pass through the at least one layer of memory structure and extend in a second direction perpendicular to the substrate surface.

Abstract: Method for manufacturing a semiconductor device includes: forming a first area and a second area of a peripheral area on a substrate; forming a first lamination structure in the first area, and forming a second lamination structure in an array area and the second area; performing thermal treatment on the substrate so that atoms in a work function layer are diffused into a second dielectric layer, and an interface interaction occurs between the second dielectric layer and a first dielectric layer; removing the first lamination structure to the second dielectric layer, and removing the second lamination structure to the second dielectric layer; forming a fourth barrier layer and a second conductive layer, a content ratio of metallic element to non-metallic element in a first barrier layer being less than a content ratio of metallic element to non-metallic element in a second barrier layer and a third barrier layer.

Abstract: The present disclosure describes techniques for social networking based on collecting asset items. Features may be extracted from an image comprising an object. The object may be associated with a location. One or more pre-stored files may be determined based on the location. The one or more pre-stored files may each correspond to one or more objects proximate to the location. Each of the one or more pre-stored files may comprise data indicative of a corresponding object. The object may be recognized based on comparing the features extracted from the image with data comprised in the one or more pre-stored files. An asset item may be received in response to recognizing the object.

Abstract: The present disclosure describes techniques for social networking based on collecting asset items. Features may be extracted from an image comprising an object and captured by a camera. The object may be associated with a location. The location may be determined based on information indicating a position where the camera is located. The object may be recognized based at least in part on the features extracted from the image. An asset item may be displayed in response to recognizing the object.

Abstract: The present disclosure describes techniques for social networking based on trading asset items. The techniques comprise sending a request by a first client computing device for connecting with a second client computing device, displaying a first video comprising a first user and a second video comprising a second user on an interface, determining a first body part of the first user based on a selection of a representative of a first asset item associated with the second user, determining a position of rendering an image of the first asset item on the interface, rendering the image of the first asset item and combining the image into the first video for display of an effect of the first asset item being tried on the first body part of the first user, and receiving the first asset item from the second user based on the effect and user input.

Abstract: A manufacturing method of a semiconductor structure includes the following operations. A substrate is provided, which includes a first N region, a first P region, a second N region and a second P region adjacently arranged in sequence. A gate dielectric layer, a first barrier layer, a first work function layer and a second barrier layer are formed on the substrate in sequence. A mask layer is formed on the second barrier layer of the first P region and the second P region. The second barrier layer of the first N region and the second N region is removed by a first etching process with the mask layer as a mask. The first work function layer and the first barrier layer of the first N region and the second N region are removed by a second etching process. A semiconductor structure is also provided.

Abstract: Provided are a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor memory. The method includes the following operations. An initial semiconductor structure is formed on a substrate. The initial semiconductor structure is etched to form an array area structure and a peripheral area structure including a peripheral area gate structure. An isolation wall surrounding the peripheral area gate structure is formed on the substrate where the peripheral area structure locates. A second dielectric layer is deposited on the peripheral area gate structure including the isolation wall and on the array area structure. The second dielectric layer, the first dielectric layer and the isolation wall are etched to form the semiconductor structure with a flat surface.

Abstract: Embodiments relate to the field of semiconductors, and provide a semiconductor structure, including a substrate and connection lines. Structural cells arranged in an array are provided on the substrate, and include transistor groups arranged in a first direction, and the transistor groups include multi-layer transistors extending in a second direction. The first direction is perpendicular to the second direction, and both are parallel to a surface of the substrate. The structural cells further include bit lines extending in a third direction, the bit lines are electrically connected to the multi-layer transistors in the same transistor group, where the third direction is perpendicular to the surface of the substrate. The connection lines are connected to the bit lines in the structural cells in one-to-one correspondence, and one bit line in the structural cells arranged in the array is connected to the same connection line.