Abstract: The present invention relates to the field of noninvasive prenatal gene testing by high-through sequencing technologies. Particularly, the present application relates to a method for determining the content of cell-free fetal DNA in maternal peripheral blood.

Abstract: A computing system includes an array of storage devices configured to store storage data and check data; and a storage engine, coupled to the array of storage devices, configured to: access the storage data, detect an erasure storage data, an erasure check data, or a combination thereof when the storage data is not accessible from the array of storage devices, and recover the storage data from the erasure storage data, the erasure check data, or the combination thereof by applying at least one of a block of check data including a slope from the check data.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.

Abstract: A computing system includes an array of storage devices configured to provide access to storage data and check data corresponding to a data block length; and a storage engine, coupled to the array of storage devices, configured to: detect one more erroneous data, one more erroneous check data, or a combination thereof for representing the storage data, the check data, or a combination thereof inaccessible or failing a status check process after initial storage thereof, determine a prime shift factor for representing a smallest prime number not less than a block unit-quantity, wherein the block unit-quantity is for representing a quantity of shift units within the data block length, and iteratively generate a target recovery set based on a circular-shift mechanism utilizing the prime shift factor for recovering the one more erroneous data, the one more erroneous check data, or a combination thereof.

Abstract: A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.

Abstract: A storage system includes: a control processor, configured to: read user data, generate a bit flip array from the user data including limiting a threshold offset range, and select an optimal read threshold set from the bit flip array; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured read a sector N with the optimal read threshold set for enhancing performance of the non-volatile memory array.

Abstract: A storage system includes: a control processor, configured to: read user data, calculate error statistics from the user data, and operate a machine learning mechanism configured to identify a bad sector based on the error statistics; and a non-volatile memory array, coupled to the control processor, configured to store the user data; and wherein the control processor is further configured to map out the bad sector, based on the machine learning mechanism, and move the user data to a target sector for enhancing performance of the non-volatile memory array.

Abstract: A storage system includes: a control processor unit, configured to: initiate a read of a raw data page, having correctable errors, calculate a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculate a correction model characterization based on the RBER (EQ1); and a non-volatile storage array, coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.

Abstract: The present disclosure provides a method and a device for driving a touch display panel, and a touch display device. The touch display panel includes L gate lines and M touch scanning lines, where L and M are each a positive integer greater than 1. The method includes steps of: dividing a time period for displaying each image frame of the touch display panel into N control time periods, each of the N control time periods including a display time period and a touch time period, N being an even number equal to or greater than 2; and driving the L gate lines within the N display time periods and driving the M touch scanning lines in each touch time period in the time period for displaying each image frame of the touch display panel.

Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.

Abstract: The present invention provides a shift register and a driving method thereof, a driving circuit, and a display device, the shift register includes an input unit, an output unit and a reset unit, the input unit controls potential of a first node according to input signals of an input terminal and a first voltage terminal, the output unit controls an output signal of an output terminal according to input signals of the input terminal and a clock signal terminal under the control of the potential of the first node, and the reset unit controls potential of a second node according to input signals of a reset terminal and a second voltage terminal.

Abstract: A storage system includes: a data storage system, configured to: load a user data block in a user data array, and link a column protection and a row protection with the user data array; and a non-volatile storage device, coupled to the data storage system, configured to store the user data block linked to the column protection and the row protection.

Abstract: The embodiments of the present disclosure provide a shift register and a method for driving the same, a gate driving circuit, and a display apparatus. The shift register comprises input circuitry, storage circuitry, output circuitry, reset circuitry, pull-down circuitry, and pull-down control circuitry. The shift register and the method for driving the same, the gate driving circuit, and the display apparatus according to the embodiments of the present disclosure can reduce noise interference.

Abstract: A computing system includes: a control circuit configured to: determine a user data, generate a base set including a base protection data based on encoding the user data according to a coding mechanism, generate an extra protection data based on encoding the user data differently from the base set according to the coding mechanism; and a storage circuit configured to store the extra protection data corresponding to the base set. The computing system can further include: an storage circuit configured to: provide a received codeword corresponding to a user data and a base protection data, provide an extra protection data corresponding to the received codeword; a control circuit configured to: decode the received codeword according to a coding mechanism, and further decode the received codeword to recover the user data based on decoding differently from decoding the base set and using the extra protection data according to the coding mechanism.

Abstract: A computing system includes: a control circuit for determining a user data, generating a base set including a base protection data based on encoding the user data, calculating an extra protection data based on encoding the base set; and a storage circuit for storing the extra protection data (210) corresponding to the base set. The computing system can further include: a storage circuit for providing a received codeword corresponding to a user data and a base protection data, providing an extra protection data corresponding to the received codeword; and a control circuit for calculating a base syndrome from the received codeword, calculating a further syndrome from the extra protection data, and decoding the received codeword to recover the user data, the base protection data, or a combination thereof using the base syndrome and the further syndrome.

Abstract: A computing system includes: storage devices configured to read data sectors; and a data correction engine, coupled to the storage devices, configured to: detect an error data sector among the data sectors, generate soft information from the error data sector, apply a soft bit flipping logic to the error data sector to produce a transformed data sector, and generate a corrected data sector from the transformed data sector.

Abstract: An array substrate (40), a driving method thereof and a display apparatus, relate to a field of display technique. The array substrate (40) comprises a plurality of pixel units (33) arranged in a matrix form and divided by a plurality of crisscrossed gate lines (31) and data lines (32), each of the pixel units (33) comprises pixel electrodes (331) and further comprises common electrodes (332); in the matrix of the pixel units (33), voltage polarities of the common electrodes (332) corresponding to pixel units (33) with a sum of numbers of rows and columns being equal are the same; voltage polarities of the common electrodes (332) of adjacent pixel units (33) are reverse. By adopting the array substrate of such a structure, the voltage swing of the data line (32) driving voltage between the positive and negative polarity gray scale is greatly reduced while the dot reversal driving is realized, thereby effectively reducing the power consumption of the array substrate (40) in the dot reversal driving mode.

Abstract: A shift register unit, includes: a first output module and a second output module, configured to output a signal of a clock signal terminal to a signal output terminal under the control of a pull-up control node; an input module, configured to output a voltage of the first power supply terminal to the pull-up control node under the control of a signal of the signal input terminal; a pull-down control module, configured to pull down a signal of the pull-down control node to a voltage of the second power supply terminal under the control of the signal input terminal; a pull-down module, configured to pull down signals of the pull-up control node and the signal output terminal to the voltage of the second power supply under the control of the pull-down control node; and a reset module, configured to output a signal of the first power supply terminal to the pull-down control node under the control of the reset signal terminal.

Abstract: A computing system includes: an interface circuit configured to provide access to a data block including an arrangement of multiple individual data; and a processing circuit, coupled to the interface circuit, configured to generate a non-orthogonal protection data corresponding to instances of the individual data along a non-orthogonal direction within the data block for correcting the one or more of the corresponding instances of the individual data.