Abstract: A computing system includes an array of storage devices configured to store storage data and check data; and a storage engine, coupled to the array of storage devices, configured to: access the storage data, detect an erasure storage data, an erasure check data, or a combination thereof when the storage data is not accessible from the array of storage devices, and recover the storage data from the erasure storage data, the erasure check data, or the combination thereof by applying at least one of a block of check data including a slope from the check data.

Abstract: There is provided a shift register unit and driving method for the shift register unit, a shift register and a display device. The shift register unit comprises a first capacitor (C1), an input buffering module (31), a pulling-up module (32), a reset control module (33), a pulling-down module (34) and a pulling-down enhancement module (35); the pulling-down module (34) is configured to reduce the level at the signal output terminal (OUTPUT) and discharge the first capacitor (C1) during a first noise-removal phase; the pulling-down enhancement module (35) is configured to control, in cooperation with the pulling-down module (34), to continuously reduce the level at the signal output terminal (OUTPUT) and continuously discharge the first capacitor (C1) during a second noise-removal phase. Noise in the output signals of the shift register can be reduced and reliability of the shift register can be improved.

Abstract: The present disclosure provides a method and a device for driving a touch display panel, and a touch display device. The touch display panel includes L gate lines and M touch scanning lines, where L and M are each a positive integer greater than 1. The method includes steps of dividing a time period for displaying each image frame of the touch display panel into N control time periods, each of the N control time periods including a display time period and a touch time period, N being an integer greater than and driving the L gate lines within the N display time periods and driving the M touch scanning lines in each touch time period in the time period for displaying each image frame of the touch display panel.

Abstract: A gate driving circuit, a display device, and a driving method are disclosed in the present invention. The gate driving circuit comprises: a plurality of cascaded shift register units and a control unit, wherein every two adjacent shift register units constitute a shift register set and are connected to two gate lines through the control unit, and wherein the control unit controls the shift register units of the shift register set to supply drive signals to the two gate lines, respectively. Embodiments of the present invention improve a configuration of the circuit on the basis of original shift registers, thereby achieving compensation of charge rations between different frames and effectively alleviating phenomena of apparent bright/dark lines such as the vertical lines of the existing products.

Abstract: A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined.

Abstract: The present invention provides a shift register and a driving method thereof, a driving circuit, and a display device, the shift register includes an input unit, an output unit and a reset unit, the input unit controls potential of a first node according to input signals of an input terminal and a first voltage terminal, the output unit controls an output signal of an output terminal according to input signals of the input terminal and a clock signal terminal under the control of the potential of the first node, and the reset unit controls potential of a second node according to input signals of a reset terminal and a second voltage terminal.

Abstract: The present disclosure discloses a gate driving circuit including multi-stage shift registers, and an output side switch element which is controlled by the second clock signal to be turned on or off. The output side switch element is located between an input terminal and an output terminal of each stage shift register. An output terminal of the (N+2)-th stage shift register is coupled to a reset terminal of the N-th stage shift register.

Abstract: A shift register unit includes an input end, a gate driving signal output end, a resetting end, a pull-up transistor, a pull-down transistor, a pull-down node control module, a pull-up node control module and an output noise reduction transistor. The pull-down node control module is configured to pull up a potential of a pull-down node to a high potential at a first noise reduction stage, so as to turn on the pull-down transistor and enable the gate driving signal output end to output a low level. The pull-up node control module is configured to pull down a potential of the pull-up node to a low potential at a resetting stage, and maintain the potential of the pull-up node to be at a low potential at the first noise reduction stage and a second noise reduction stage, so as to turn off the pull-up transistor.

Abstract: A method is disclosed for performing LDPC decoding, specifically layered min-sum decoding using a Tanner graph including check nodes (CN) and variable nodes (VN). Messages passed between nodes are quantized in a non-uniform manner. Values below a threshold are uniformly quantized whereas values above the threshold are non-uniformly quantized. A corresponding inverse-quantization is also defined.

Abstract: There is provided a shift register unit and driving method for the shift register unit, a shift register and a display device.

Abstract: A gate driving circuit, a display device, and a driving method are disclosed in the present invention. The gate driving circuit comprises: a plurality of cascaded shift register units and a control unit, wherein every two adjacent shift register units constitute a shift register set and are connected to two gate lines through the control unit, and wherein the control unit controls the shift register units of the shift register set to supply drive signals to the two gate lines, respectively. Embodiments of the present invention improve a configuration of the circuit on the basis of original shift registers, thereby achieving compensation of charge rations between different frames and effectively alleviating phenomena of apparent bright/dark lines such as the vertical lines of the existing products.

Abstract: An array substrate (40), a driving method thereof and a display apparatus, relate to a field of display technique. The array substrate (40) comprises a plurality of pixel units (33) arranged in a matrix form and divided by a plurality of crisscrossed gate lines (31) and data lines (32), each of the pixel units (33) comprises pixel electrodes (331) and further comprises common electrodes (332); in the matrix of the pixel units (33), voltage polarities of the common electrodes (332) corresponding to pixel units (33) with a sum of numbers of rows and columns being equal are the same; voltage polarities of the common electrodes (332) of adjacent pixel units (33) are reverse. By adopting the array substrate of such a structure, the voltage swing of the data line (32) driving voltage between the positive and negative polarity gray scale is greatly reduced while the dot reversal driving is realized, thereby effectively reducing the power consumption of the array substrate (40) in the dot reversal driving mode.

Abstract: The present disclosure discloses a gate driving circuit including multi-stage shift registers, and an output side switch element which is controlled by the second clock signal to be turned on or off. The output side switch element is located between an input terminal and an output terminal of each stage shift register. An output terminal of the (N+2)-th stage shift register is coupled to a reset terminal of the N-th stage shift register.

Abstract: The present invention relates generally to a device and method for supplying a sorbent, at one or more various desired supply points in a flue gas stream, to boilers, heaters, kilns, or other flue gas-, or combustion gas-, generating devices (e.g., those located at power plants, processing plants, etc.). In one embodiment, the device of the present invention that is designed to supply a sorbent comprises a series of coaxial pipes. In another embodiment, the device of the present invention that is designed to supply a sorbent comprises a mixing section with a plurality of distribution vanes contained in at least one mixing section.

Abstract: The present invention relates generally to a device and method for supplying a sorbent, at one or more various desired supply points in a flue gas stream, to boilers, heaters, kilns, or other flue gas-, or combustion gas-, generating devices (e.g., those located at power plants, processing plants, etc.). In one embodiment, the device of the present invention that is designed to supply a sorbent comprises a series of coaxial pipes. In another embodiment, the device of the present invention that is designed to supply a sorbent comprises a mixing section with a plurality of distribution vanes contained in at least one mixing section.