Abstract: A double-sided display and a method for controlling the same are provided. The double-sided display includes a plurality of pixel units and a plurality of circuits. The pixel units are disposed on each of a front side and a back side of the double-sided display, and the pixel units on the front side are opposite to the pixel units on the back side in a one-to-one manner. A pixel unit on the front side and a pixel unit on the back side opposite to the pixel unit on the front side are controlled by an identical circuit. Each of the circuits includes a switching transistor. The switching transistor includes a first input terminal connected to a scan line, a second input terminal connected to a data line, and an output terminal connected to the opposite pixel units on the front side and the back side.

Abstract: A substrate-less display device is disclosed. The substrate-less display device includes a barrier stack. The barrier stack includes a plurality of inorganic barrier films and a plurality of polymer films. The inorganic barrier films and the polymer films are alternatively disposed. The substrate-less display device further includes a thin-film-transistor (TFT) device layer disposed on the barrier stack, a display medium layer disposed on the TFT device layer, and an encapsulation layer disposed on the display medium layer.

Abstract: The present invention is applicable to the field of display technologies and provides a tiled OLED display, and the tiled OLED display includes an OLED front panel and a single-structure TFT driving backplane, where a protection substrate is disposed on a light-emitting side of the OLED front panel; the OLED front panel includes multiple OLED front panel units that are tiled to each other; and the OLED front panel unit is joined to the TFT driving backplane by using conductive film. In the present invention, by tiling the OLED front panel on the TFT backplane, production efficiency and a yield rate of the display are improved, thereby reducing a cost. By tiling the OLED front panel, a tiling gap is narrowed, thereby implementing seamless tiling. Compared with a traditional structure that uses an optical lens to eliminate a tiling gap, the yield rate of the tiled display is improved.

Abstract: A nerve guidance conduit includes a spiral structured porous sheet decorated with channels on its surface and electrospun nanofibers in a parallel alignment with the channels and an outer tubular structure including randomly-oriented nanofibers. Such a structure provides augmented surface areas for providing directional guidance and augmented surfaces for enhancing and peripheral nerve regeneration. The structure also has the mechanical and nutrient transport requirements required over long regeneration periods. To prepare a nerve guidance conduit, porous polymer sheet is prepared by a solvent casting method while using a template of thin rods to form parallel channels on a surface of the sheet. Aligned nanofibers are deposited on the sheet parallel to the channels. The polymer sheet is then wound to form a spiral structure. A dense layer of randomly-oriented nanofibers may be deposited on the outside of the spiral.

Abstract: The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate, wherein the metal oxide layer is in a thin film transistor region; through a same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate for forming a gate region, source and drain regions for forming contact vias, a gate interface region, and a storage capacitor region, respectively. Through additional steps including etching, metallizing, and filling, a source contact via is formed in the source region, a drain contact via is formed in the drain region, and a connecting contact via is formed in the gate interface region, respectively.

Abstract: The present application provides a method for preparing a rare-earth permanent magnetic material with grain boundary diffusion using composite target by vapor deposition, in which the composite target is evaporated and attached to the surface of the NdFeB magnet, and in which medium-high temperature treatment and low temperature aging treatment are employed, resulting in that the coercive force of the magnet is improved significantly and the remanence and the magnetic energy product substantially are not reduced. The advantageous effects of the present application is as follows: the coercive force of the magnet is improved, and meanwhile the defects such as melting pits and crystal grain growth and the like caused by high temperature treatment for the long time are eliminated, and the usage amount of heavy rare-earth is greatly reduced, thereby lowering the cost of the product.

Abstract: The present invention is applicable to the field of electronic component technologies and provides a manufacturing method of a self-aligned metal oxide TFT component, including: selecting a substrate and preparing a gate on the substrate; successively disposing an insulation layer, a transparent electrode layer, and a photoresist on the gate; using the gate as a mask to perform exposure from a back side of the substrate, so as to form a source and a drain that are aligned with the gate; depositing a metal oxide semiconductor layer on the transparent electrode layer; performing etching on the semiconductor layer, the source, and the drain, so that outer ends of the source and the drain are exposed out of the metal oxide semiconductor layer; and depositing a passivation layer and leading out the source and the drain.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause a change in a charge storage layer included in the first transistor.

Abstract: A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate.

Abstract: Systems, methods, and apparatus are disclosed for implementing memory cells having common source lines. The methods may include receiving a first voltage at a first transistor. The first transistor may be coupled to a second transistor and included in a first memory cell. The methods include receiving a second voltage at a third transistor. The third transistor may be coupled to a fourth transistor and included in a second memory cell. The first and second memory cells may be coupled to a common source line. The methods include receiving a third voltage at a gate of the second transistor and a gate of the fourth transistor that may cause them to operate in cutoff mode. The methods may include receiving a fourth voltage at a gate of the first transistor. The fourth voltage may cause, via Fowler-Nordheim tunneling, a change in a charge storage layer included in the first transistor.

Abstract: A memory structure including a memory array of a plurality of memory cells arranged in rows and columns, the plurality of memory cells including a pair of adjacent memory cells in a row of the memory array, wherein the pair of adjacent memory cells include a single, shared source-line through which each of the memory cells in the pair of adjacent memory cells is coupled to a voltage source. Methods of operating a memory including the memory structure are also described.

Abstract: A method including forming a structure including a plurality of semiconductor devices surrounded by a dielectric layer such that a top surface of the dielectric layer is substantially flush with a top surface of the plurality of semiconductor devices, depositing a thermal optimization layer above the structure, patterning the thermal optimization layer such that a portion of the thermal optimization layer is removed from a above first region of the structure and another portion of the thermal optimization layer remains above a second region of the structure, the first region having a different thermal conductivity than the second region, and heating the structure, the patterned thermal optimization layer causing substantially uniform thermal absorption of the structure.

Abstract: In one embodiment, a semiconductor device is provided that includes a semiconductor substrate including an active region and at least one trench isolation region at a perimeter of the active region, and a functional gate structure present on a portion of the active region of the semiconductor substrate. Embedded semiconductor regions are present in the active region of the semiconductor substrate on opposing sides of the portion of the active region that the functional gate structure is present on. A portion of the active region of the semiconductor substrate separates the outermost edge of the embedded semiconductor regions from the at least one isolation region. Methods of forming the aforementioned device are also provided.

Abstract: The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate, wherein the metal oxide layer is in a thin film transistor region; through a same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate for forming a gate region, source and drain regions for forming contact vias, a gate interface region, and a storage capacitor region, respectively. Through additional steps including etching, metallizing, and filling, a source contact via is formed in the source region, a drain contact via is formed in the drain region, and a connecting contact via is formed in the gate interface region, respectively.

Abstract: A substrate-less display device is disclosed. The substrate-less display device includes a barrier stack. The barrier stack includes a plurality of inorganic barrier films and a plurality of polymer films. The inorganic barrier films and the polymer films are alternatively disposed. The substrate-less display device further includes a thin-film-transistor (TFT) device layer disposed on the barrier stack, a display medium layer disposed on the TFT device layer, and an encapsulation layer disposed on the display medium layer.

Abstract: A thin film transistor (TFT) device is provided. The TFT device includes a first conductive layer including a gate electrode and a connection pad. The TFT device further includes a first dielectric layer covering the gate electrode, and a semiconductor layer disposed on the dielectric layer and overlapping the gate electrode. The TFT device further includes a second dielectric layer disposed on the semiconductor layer and the first dielectric layer so as to expose first and second portions of the semiconductor layer and the connection pad. The TFT device further includes a second conductive layer which includes a source electrode portion covering the first portion of the semiconductor layer; a pixel electrode portion extending to the source electrode portion; a drain electrode portion covering the second portion of the semiconductor layer; and an interconnection portion disposed on the connection pad and extending to the drain electrode portion.

Abstract: The present invention provides a method of manufacturing a thin film transistor and a pixel unit thereof, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate; through the same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, while retaining: the metal oxide layer, the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and the part of the metal oxide layer, the gate insulating layer and the gate metal layer in source and drain regions for forming contact vias; and exposing the remaining metal oxide layer in the source region and in the drain region; depositing a passivation layer, etching and metallizing the exposed oxide in the source and drain regions to form the source and drain contact vias.

Abstract: The present invention is suitable to the field of electronic technology, and provides a method of manufacturing a thin film transistor and a pixel unit thereof, wherein when the thin film transistor is manufactured, the gate metal layer is used as a mask, and exposed from the back of the substrate to position the channel and the source and drain of the thin film transistor, so that the channel is self-aligned with the gate, and the source and drain are self-aligned with the gate and are symmetrical, and the thin film transistor thus manufactured has a small parasitic capacitance, and the circuit manufactured therewith is fast in operation, and less prone to occurring short circuit or open circuit.

Abstract: The present invention relates to the field of electronic device fabrication, provides a method for fabricating a flexible electronic device, and is intended to address the problems present in the prior art that the adhesive cannot be completely peeled off and the flexible substrate is damaged during peeling the flexible substrate from the rigid substrate in the flexible electronic device fabrication. The fabrication method comprises providing a channel on a rigid substrate; adhering a flexible substrate to the rigid substrate with an adhesive; fabricating an electronic device on the flexible substrate; injecting a chemical substance into the channel; and reacting the chemical substance with the adhesive, and peeling the flexible substrate from the rigid substrate. The present invention also provides a substrate for fabricating a flexible electronic device.

Abstract: The present invention provides a method of manufacturing a thin film transistor and a pixel unit thereof, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate; through the same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, while retaining: the metal oxide layer, the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and the part of the metal oxide layer, the gate insulating layer and the gate metal layer in source and drain regions for forming contact vias; and exposing the remaining metal oxide layer in the source region and in the drain region; depositing a passivation layer, etching and metallizing the exposed oxide in the source and drain regions to form the source and drain contact vias.