Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: Improved magnesium diboride superconducting materials and methods of synthesis are disclosed. Embodiments of the superconducting material comprise at least two starting materials capable of forming MgB2 and at least one dopant compound comprising silicon, carbon, hydrogen and oxygen. The starting materials and the at least one dopant compound are heated and mixed at an atomic level to produce a silicon-doped MgB2 superconducting material. Examples of the dopant compound include silicone oil, Triacetoxy(methyl)silane (2), 1,7-Dichloro-octamethyltetrasiloxane (2) and Tetramethyl orthosilicate (6).

Abstract: The present invention relates to a method for the preparation of (3S,4S)-3-hexyl-4-((R)-2-hydroxytridecyl)-oxetan-2-one and a product of the method. The method includes the following steps: a) reducing a substance represented by formula (II) to obtain a substance represented by formula (III), and then oxidizing the substance represented by formula (III) to form a substance represented by formula (IV); b) acylating n-octanoic acid to obtain n-octanoyl chloride using thionyl dichloride, then condensing the obtained n-octanoyl chloride with 2-mercapto-pyridine under basic condition to form a substance represented by formula (V), and then converting the substance represented by formula (V) to a substance represented by formula (VI); c) reacting the substance obtained in the step a) with the substance obtained in the step b) under catalytic condition of Lewis acid to generate a substance represented by formula (VII), and then reacting with a Lewis acid.

Abstract: The present disclosure provides a new type of gapless semiconductor material having electronic properties that can be characterized by an electronic band structure which comprises valence and conduction band portions VB1 and CB1, respectively, for a first electron spin polarisation, and valence and conducting band portions VB2 and CB2, respectively, for a second electron spin polarisation. The valence band portion VB1 has a first energy level and one of CB1 and CB2 have a second energy level that are positioned so that gapless electronic transitions are possible between VB1 and the one of CB1 and CB2, and wherein the gapless semiconductor material is arranged so that an energy bandgap is defined between VB2 and the other one of CB1 and CB2.

Abstract: A method of location positioning of a Radio Access Point (AP) is provided in an embodiment of the present invention. The method includes: querying the Connectivity Session Location and Repository Function (CLF) according to the IP address of the AP to obtain the Access Line Location Identifier (ALLI) of the AP to access a network. The ALLI is configured to identify the line location of the AP. The location of the AP is determined on the basis of the ALLI. A method of location verification of an AP is provided herein in an embodiment of the present invention. The method includes: the CLF is queried according to the IP address of the AP to obtain the ALLI of the AP; the location of the AP is not changed if the obtained ALLI of the AP is the same as the stored ALLI of the AP. A home register and a system are also provided herein to accurately locate and verify the location of the AP, thus checking the validity of the AP location.

Abstract: Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing wherein each functional unit has its own instruction fetch and decode block, and each functional unit has its own local memory for program storage; and wherein computational hardware execution units and memory units are flexibly pipelined as programmable embedded processors with reconfigurable pipeline stages of different order in response to varying application instruction sequences that establish different configurations and switching interconnections of the hardware units.

Abstract: The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast as every clock cycle based on the instruction sequence in an application program preloaded into the processor, and wherein the processor includes a data switch matrix selectively and flexibly interconnecting pluralities of mathematical execution units and memory units in response to said instructions, and wherein the execution units are configurable to perform operations at different precisions of multi-bit arithmetic and logic operations and in a multi-level hierarchical architecture structure.

Abstract: A configurable adaptive variable length data packet transmission output scheduler for enabling substantially simultaneous transmission on a common transmission link, as of fiber optics, of differentiated services for various different traffic types, executing different QOS algorithms while co-existing in a converged network environment, with simultaneous preserving of the different service characteristics for real-time or high-priority traffic and providing differentiated bandwidth allocation while achieving maximal link utilization—all through a fine and balanced control as to which type of traffic is transmitted on the link for a given duration, and how much of that traffic is transmitted on the link.

Abstract: A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured by software for each specific application by communication through a switch fabric in a dynamic, parallel and flexible fashion to achieve a reconfigurable pipeline, wherein the length of the pipeline stages and the order of the stages varies from time to time and from application to application, admirably handling the explosion of varieties of diverse signal processing needs in single devices such as handsets, set-top boxes and the like with unprecedented performance, cost and power savings, and with full application flexibility.

Abstract: A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Abstract: A novel scalable-port non-blocking shared-memory output-buffered variable length queued data switching method and apparatus wherein successive data in each of a plurality of queues of data traffic is distributed to corresponding cells of each of successive memory channels in striped fashion across a shared memory space.

Abstract: In the routing of data traffic to a common destination egress queue from a plurality of customer subscribers each contracting for respective allocations of bandwidth of data flow, a technique and system for fairly sharing any underutilized excess bandwidth and for data dropping amongst over-subscribers, while guaranteeing each subscriber its contracted-for bandwidth, and further enabling billing over-subscribers for their share of received excess bandwidth—all while maintaining the granularity of the contracted traffic flow.

Abstract: A configurable adaptive variable length data packet transmission output scheduler for enabling substantially simultaneous transmission on a common transmission link, as of fiber optics, of differentiated services for various different traffic types, executing different QOS algorithms while co-existing in a converged network environment, with simultaneous preserving of the different service characteristics for real-time or high-priority traffic and providing differentiated bandwidth allocation while achieving maximal link utilization—all through a fine and balanced control as to which type of traffic is transmitted on the link for a given duration, and how much of that traffic is transmitted on the link.

Abstract: A single integrated wafer may be formed with optical components on one side and electronic components on the opposite side. Communication between the sides may be by way of optical signals that may be transmitted through the semiconductor wafer.

Abstract: A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Abstract: A novel fault-tolerance technique for protecting against and correcting errors in packet data stream flow, preferably through not exclusively with closed ring sequential address generators and the like, through the use of pairs of independent but linked packet data flow paths enabling discarding of error data occurring in one path and substituting therefor corresponding correct data from the other path to enable continuation of the data stream flow without interruption and without error.

Abstract: A sequential data packet addressing technique and system, particularly adapted for shared memory output-buffered switch fabrics and related memories, using a ring of successive subaddress generators each assigning addresses for predetermined size data byte packets received in successive time slots, and creating therefrom super packets ordered based on arrival time; and sequentially allocating memory therefor in the shared memory without overlap among the packets and with no holes between adjacent packets, and assigning addresses for the individual packets in the super packets upon the assigning of an address in the memory for each super packet.

Abstract: A novel scalable-port non-blocking shared-memory output-buffered variable length queued data switching method and apparatus.