Abstract: A method for manufacturing a semiconductor device comprises, including forming a plurality of fins on a substrate, forming, a dummy gate stack on the fins forming a gate spacer on opposite sides of the dummy gate stack, forming source/drain trenches by etching the fins with the gate spacer and the dummy gate stack as a mask, forming source/drain extension regions on the bottom and sides of the trenches by performing lightly-doping ion implantation; and by performing epitaxial growth in and/or on the source/drain trenches, removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract: The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved.

Abstract: A method for manufacturing a semiconductor device comprises: forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; etching the fins with the gate spacer and the dummy gate stack as a mask, to form source/drain trenches; performing lightly-doping ion implantation to form source/drain extension regions on bottom and side walls of the source/drain trenches; performing epitaxial growth in and/or on the source/drain trenches to form source/drain regions; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming, on a substrate, a plurality of fins extending along a first direction; forming, on the fins, a dummy gate stack extending along a second direction; forming a gate spacer on opposite sides of the dummy gate stack in the first direction; epitaxially growing raised source/drain regions on the top of the fins on opposite sides of the gate spacer in the first direction; performing lightly-doping ion implantation through the raised source/drain regions with the gate spacer as a mask, to form source/drain extension regions in the fins on opposite sides of the gate spacer in the first direction; removing the dummy gate stack to form a gate trench; and forming a gate stack in the gate trench.

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

Abstract: A semiconductor device includes a fin extending on a substrate along a first direction; a gate extending along a second direction across the fin; and source/drain regions and a gate spacer on the fin at opposite sides of the gate, in which there is a surface layer on the top and/or sidewalls of the fin.

Abstract: A FinFET device and a method for manufacturing the same. The FinFET device includes a plurality of fins each extending in a first direction on a substrate; a plurality of gate stacks each being disposed astride the plurality of fins and extending in a second direction; a plurality of source/drain region pairs, respective source/drain regions of each source/drain region pair being disposed on opposite sides of the each gate stack in the second direction; and a plurality of channel regions each comprising a portion of a corresponding fin between the respective source/drain regions of a corresponding source/drain pair, wherein the each fin comprises a plurality of protruding cells on opposite side surfaces in the second direction.

Abstract: The present invention provides to an in-plane-switching (IPS) mode liquid crystal panel, which comprises: a first substrate, a second substrate, a coplanar transparent electrode layer and a liquid crystal layer. The first and second substrates have a first alignment film and a second alignment film, respectively. The coplanar transparent electrode layer is disposed onto the second alignment film. The liquid crystal layer is disposed in a space between the first alignment film of the first substrate and the coplanar transparent electrode layer of the second substrate. The liquid crystal layer comprises dual-frequency liquid crystal molecules and dual-frequency reactive mesogens/monomers. The liquid crystal panel of the present invention can overcome the problems of pollution and static electricity generated from the rubbing alignment in the in-plane-switching (IPS) mode, so as to simplify the manufacturing process and provide the advantages of high contrast, high response speed and wide viewing angle.

Abstract: A liquid crystal medium composition of liquid crystal display includes: a negative liquid crystal material, reactive monomer, an initiator, and a stabilizer. The initiator functions to induce photo polymerization of the reactive monomer. The initiator has a molecular structure comprising aromatic rings, carbonyl groups connected to the aromatic rings, and substituted moieties connected to the aromatic rings. The initiator lowers the activation energy of chain initiation reaction of the polymerization of reactive monomer to allow the photo polymerization of the reactive monomer to take place in a wider wavelength range of 200-450 nm, so as to reduce the required intensity and luminance of ultraviolet light and to speed up the reaction of the reactive monomers and also to provide a uniform result of reaction, to reduce the destruction that the ultraviolet light causes on the material of alignment layer and the liquid crystal material, and to improve stability of the panel.

Abstract: Methods of manufacturing stacked nanowires MOS transistors are disclosed. In one aspect, the method includes forming a plurality of fins along a first direction on a substrate. The method also includes forming stack of nanowires constituted of a plurality of nanowires in each of the fins. The method also includes forming a gate stack along a second direction in the stack of nanowires, the gate stack surrounding the stack of nanowires. The method also includes forming source/drain regions at both sides of the gate stack, the nanowires between the respective source/drain regions constituting a channel region. A stack of nanowires may be formed by a plurality of etching back, laterally etching a trench and filling the trench. The laterally etching process includes isotropic dry etching having an internally tangent and lateral etching, and a wet etching which selectively etches along respective crystallographic directions.

Abstract: The present invention discloses a semiconductor device, which comprises a substrate, a gate stack structure on the substrate, a channel region in the substrate under the gate stack structure, and source and drain regions at both sides of the channel region, wherein there is a stressed layer under and at both sides of the channel region, in which the source and drain regions are formed. According to the semiconductor device and the method for manufacturing the same of the present invention, a stressed layer is formed at both sides of and under the channel region made of a silicon-based material so as to act on the channel region, thereby effectively increasing the carrier mobility of the channel region and improving the device performance.

Abstract: The invention provides an LCD panel, an LCD device, and a method for manufacturing a panel. The LCD panel includes an upper substrate and a lower substrate which are arranged opposite to each other. Opposite inner sides of the upper substrate and the lower substrate are respectively provided with a layer of alignment film, a sealant is arranged between the upper substrate and the lower substrate, the alignment film is arranged to extend outside the sealant area, and a surface of the alignment film exposed outside the sealant is provided with a sealing layer. In the invention, the alignment film is arranged to extend outside the sealant, which enable a narrow frame to be used to the LCD panel, and improves the utilization rate of the substrate; moreover, the alignment film exposed outside the sealant is sealed, to completely isolate the alignment film from the outside air; thus, the alignment film cannot be hydrolyzed because of absorbing the outside vapor, thereby ensuring the display quality.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, which comprises: forming a plurality of fins on a substrate, which extend along a first direction and have rhombus-like cross-sections; forming a gate stack structure on each fin, which traverses the plurality of fins and extends along a second direction; wherein a portion in each fin that is under the gate stack structure forms a channel region of the device, and portions in each fin that are at both sides of the gate stack structure along the first direction form source and drain regions. The semiconductor device and its manufacturing method according to the present invention use rhombus-like fins to improve the gate control capability to effectively suppress the short channel effect, moreover, an epitaxial quantum well is used therein to better limit the carriers, thus improving the device drive capability.

Abstract: The present invention provides a semiconductor structure comprising a substrate; a gate stack on the substrate; a spacer on the sidewalls of the gate stack; a source/drain junction extension formed in the substrate on both sides of the gate stack by epitaxial growth; and a source/drain region in the substrate on both sides of the source/drain junction extension. Accordingly, the present invention also provides methods for manufacturing the semiconductor structure. The present invention can provide a source/drain junction extension with a high doping concentration and a low junction depth, thereby effectively improving the performance of the semiconductor structure.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region.

Abstract: The present invention provides a TFT-LCD array substrate having a gate-line metal layer, a data-line metal layer crossing the gate-line metal layer and a plurality of layers covering a periphery of the gate-line metal layer and the data-line metal layer; the gate-line metal layer has first gate lines and second gate lines parallel and alternately arranged, the date-line metal layer has first data lines and second data lines parallel and alternately arranged; the first gate line and the second gate line are electrically connected; the first data line and the second data line are electrically connected. The present invention further provides a manufacturing method of the TFT-LCD array substrate. Implementing the TFT-LCD array substrate and the manufacturing method can reduce the occurrence of line-broken in the active array of TFT-LCD, increase the aperture ratio of the product and enhance yield rate of the products.

Abstract: The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a gate stack structure on a substrate; forming a drain region in the substrate on one side of the gate stack structure; and forming a source region made of GeSn in the substrate on the other side of the gate stack structure; wherein the forming the source region made of GeSn comprises: implanting precursors in the substrate on the other side of the gate stack structure; and performing a laser rapid annealing such that the precursors react to produce GeSn alloy, thereby to constitute a source region; and wherein the step of implanting precursors further comprises: performing a pre-amorphization ion implantation, so as to form an amorphized region in the substrate; and implanting Sn in the amorphized region.

Abstract: The present invention discloses a semiconductor device, comprising: a substrate, a gate stack structure on the substrate, source and drain regions in the substrate on both sides of the gate stack structure, and a channel region between the source and drain regions in the substrate, characterized in that at least one of the source and drain regions comprises a GeSn alloy. In accordance with the semiconductor device and method for manufacturing the same of the present invention, GeSn stressed source and drain regions with high concentration of Sn is formed by implanting precursors and performing a laser rapid annealing, thus the device carrier mobility of the channel region is effectively enhanced and the device drive capability is further improved.

Abstract: A method for manufacturing a semiconductor device is disclosed. In one aspect the method includes forming a gate stack over a substrate. The method also includes forming a dummy sidewall spacer around the gate stack. The method also includes depositing a stress liner of diamond-like amorphous carbon (DLC) on the substrate, the gate stack and the dummy sidewall spacer. The method also includes annealing, so that a channel region in the substrate below the gate stack and the gate stack memorize stress in the stress liner. The method also includes removing the dummy sidewall spacer. The method also includes forming a sidewall spacer around the gate stack. In the method according to the disclosed technology, large stress in the liner of DLC is memorized and applied to the dummy gate stack and the channel region to increase carrier mobility and improve performances of the device.