Patents by Inventor Xiaomeng Chen

Xiaomeng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11359089
    Abstract: Disclosed in the present invention is a method for preparing a Y-branched hydrophilic polymer carboxylic acid derivative, in particular a method for preparing a Y-branched polyethylene glycol carboxylic acid derivative having a high purity and high molecular weight. The preparation steps are simple, the product of the reaction is easy to be separated, the cost for separation is low, and the purity and yield of the product are high, facilitating the subsequent preparation of other derivatives and medicament conjugates based on the preparation of the carboxylic acid derivative, which is advantageous for industrial scale-up and commercial applications. The prepared Y-branched hydrophilic polymer carboxylic acid derivative (in particular the Y-branched polyethylene glycol carboxylic acid derivative having a high molecular weight) product has a high purity and high commercial application value, in particular in the use of the preparation of medicaments for preventing and/or treating diseases.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 14, 2022
    Assignee: JENKEM TECHNOLOGY CO., LTD. (BEIJING)
    Inventors: Xiaomeng Chen, Meina Lin, Rujun Zhang, Xuan Zhao
  • Publication number: 20220183074
    Abstract: A random access method and an apparatus. In the method, random access is completed in a manner in which an agent terminal performs access, so that an access requirement of a terminal can be satisfied under low energy consumption. The method and the apparatus may be applied to application scenarios such as an internet of things (IoT), machine type communication (MTC), massive machine type communication (mMTC), an internet of vehicles, and a connected vehicle.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yunhao ZHANG, Xiaomeng CHAI, Yang CHEN
  • Patent number: 11282697
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11281252
    Abstract: A liquid crystal display (LCD) includes several transparent material layers and several non-transparent material layers that are disposed in a stacked mode. The LCD also has a local transparent region, and no non-transparent material is applied to the several non-transparent material layers in the local transparent region. This forms a transparent channel in the local transparent region along a stacking direction. An optical component is completely or partially disposed in the transparent channel of the LCD display. The optical component may be a camera, an ambient light sensor, an optical fingerprint sensor, or another component disposed under the display by using the local transparent region on the LCD display.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 22, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bangshi Yin, Fan Yang, Bin Yan, Kangle Xue, Xiaomeng Chen
  • Patent number: 11276587
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11231376
    Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.
    Type: Grant
    Filed: April 15, 2020
    Date of Patent: January 25, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chien-Huei Chen, Hung-Yi Chung, Xiaomeng Chen
  • Patent number: 11222896
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 11, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Publication number: 20210397215
    Abstract: A liquid crystal display (LCD) includes several transparent material layers and several non-transparent material layers that are disposed in a stacked mode. The LCD also a local transparent region, and no non-transparent material is applied to the several non-transparent material layers in the local transparent region. This forms a transparent channel in the local transparent region along a stacking direction. An optical component is completely or partially disposed in the transparent channel of the LCD display. The optical component may be a camera, an ambient light sensor, an optical fingerprint sensor, or another component disposed under the display by using the local transparent region on the LCD display.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 23, 2021
    Inventors: Bangshi Yin, Fan Yang, Bin Yan, Kangle Xue, Xiaomeng Chen
  • Publication number: 20210305292
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20210272964
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11048294
    Abstract: A liquid crystal display (LCD), an electronic device, and an LCD manufacturing method, where the LCD includes transparent material layers and non-transparent material layers that are disposed in a stacked mode. There is a local transparent region on the LCD. A non-transparent material is applied to the several non-transparent material layers in the local transparent region to form a transparent channel in the local transparent region along a stacking direction. An optical component such as a camera, an ambient light sensor, or an optical fingerprint sensor is completely or partially disposed in the transparent channel of the LCD display.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: June 29, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Bangshi Yin, Fan Yang, Bin Yan, Kangle Xue, Xiaomeng Chen
  • Patent number: 11037932
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 11037978
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20210151353
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11011524
    Abstract: A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 10998494
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20210118125
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Publication number: 20210063319
    Abstract: A method for semiconductor wafer inspection is provided. The method includes the following operations. The semiconductor wafer is scanned to acquire a scanned map, wherein the semiconductor wafer is patterned according to a design map having a programmed defect. The design map and the scanned map are transformed to a transformed inspection map according to the location of the programmed defect on the design map and the location of the programmed defect on the scanned map. The system of semiconductor wafer inspection is also provided.
    Type: Application
    Filed: April 15, 2020
    Publication date: March 4, 2021
    Inventors: CHIEN-HUEI CHEN, HUNG-YI CHUNG, XIAOMENG CHEN
  • Publication number: 20210013098
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20210014420
    Abstract: An intelligent assistant control method is provided: starting, by a terminal device, a lens; displaying, by the terminal device, a preview interface on a display screen, where the preview interface includes a to-be-photographed object; and if the terminal device determines that the preview interface has been stably displayed for preset duration, displaying, by the terminal device, first prompt information of a photographing mode in the preview interface, where the first prompt information is used to recommend a first photographing mode to a user, and the first photographing mode is determined by the terminal device based on scene information of the to-be-photographed object.
    Type: Application
    Filed: March 26, 2018
    Publication date: January 14, 2021
    Inventors: Lei SONG, Xin GUO, Xiaomeng CHEN, Yunchao ZHANG, Xin CHEN