Patents by Inventor Xiaomeng Chen

Xiaomeng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790189
    Abstract: An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
    Type: Grant
    Filed: October 2, 2018
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsun-Chung Kuang, Yen-Chang Chu, Cheng-Tai Hsiao, Ping-Yin Liu, Lan-Lin Chao, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10756222
    Abstract: A photo-sensitive device includes a uniform layer, a gradated buffer layer over the uniform layer, a silicon layer over the gradated buffer layer, a photo-sensitive light-sensing region in the uniform layer and the silicon layer, a device layer on the silicon layer, and a carrier wafer bonded to the device layer.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: August 25, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Hung Cheng, Chia-Shiung Tsai, Cheng-Ta Wu, Xiaomeng Chen, Yen-Chang Chu, Yeur-Luen Tu
  • Patent number: 10665449
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200117034
    Abstract: A liquid crystal display (LCD), an electronic device, and an LCD manufacturing method, where the LCD includes transparent material layers and several non-transparent material layers that are disposed in a stacked mode. There is a local transparent region on the LCD. A non-transparent material is applied to the several non-transparent material layers in the local transparent region to form a transparent channel in the local transparent region along a stacking direction. An optical component such as a camera, an ambient light sensor, or an optical fingerprint sensor is completely or partially disposed in the transparent channel of the LCD display.
    Type: Application
    Filed: June 26, 2017
    Publication date: April 16, 2020
    Applicant: Huawei Technologies Co., Ltd.
    Inventors: Bangshi YIN, Fan YANG, Bin YAN, Kangle XUE, Xiaomeng CHEN
  • Publication number: 20200105548
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Application
    Filed: November 19, 2019
    Publication date: April 2, 2020
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200075600
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Application
    Filed: November 8, 2019
    Publication date: March 5, 2020
    Inventors: Chern-Yow HSU, Chen-Jong WANG, Chia-Shiung TSAI, Ming Chyi LIU, Shih-Chang LIU, Xiaomeng CHEN
  • Publication number: 20200052014
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20200024446
    Abstract: Disclosed in the present invention is a method for preparing a Y-branched hydrophilic polymer carboxylic acid derivative, in particular a method for preparing a Y-branched polyethylene glycol carboxylic acid derivative having a high purity and high molecular weight. The preparation steps are simple, the product of the reaction is easy to be separated, the cost for separation is low, and the purity and yield of the product are high, facilitating the subsequent preparation of other derivatives and medicament conjugates based on the preparation of the carboxylic acid derivative, which is advantageous for industrial scale-up and commercial applications. The prepared Y-branched hydrophilic polymer carboxylic acid derivative (in particular the Y-branched polyethylene glycol carboxylic acid derivative having a high molecular weight) product has a high purity and high commercial application value, in particular in the use of the preparation of medicaments for preventing and/or treating diseases.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Xiaomeng CHEN, Meina LIN, Rujun ZHANG, Xuan ZHAO
  • Publication number: 20200028070
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Publication number: 20200006052
    Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Inventors: Xin-Hua Huang, Ping-Yin Liu, Hung-Hua Lin, Hsun-Chung Kuang, Yuan-Chih Hsieh, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10504756
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10504904
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chern-Yow Hsu, Chen-Jong Wang, Chia-Shiung Tsai, Ming Chyi Liu, Shih-Chang Liu, Xiaomeng Chen
  • Patent number: 10497860
    Abstract: Some embodiments of the present disclosure relate to a method that achieves a substantially uniform pattern of magnetic random access memory (MRAM) cells with a minimum dimension below the lower resolution limit of some optical lithography techniques. A copolymer solution comprising first and second polymer species is spin-coated over a heterostructure which resides over a surface of a substrate. The heterostructure comprises first and second ferromagnetic layers which are separated by an insulating layer. The copolymer solution is subjected to self-assembly into a phase-separated material comprising a pattern of micro-domains of the second polymer species within a polymer matrix comprising the first polymer species. The first polymer species is then removed, leaving a pattern of micro-domains of the second polymer species. A pattern of magnetic memory cells within the heterostructure is formed by etching through the heterostructure while utilizing the pattern of micro-domains as a hardmask.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: December 3, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Ming Chen, Chern-Yow Hsu, Szu-Yu Wang, Chung-Yi Yu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 10464882
    Abstract: The present invention discloses a Y-type discrete polyethylene glycol derivative, which has the advantages of determined molecular weights and the number of chain segments, and can avoid the defect of heterogeneity of a PEG derivative. In addition, the Y-type discrete polyethylene glycol derivative of the present invention may increase the water solubility of the discrete polyethylene glycol, and solve the problem of insufficient water solubility of the discrete polyethylene glycol-modified insoluble drug caused by an increase of the loading capacity.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: November 5, 2019
    Assignee: JENKEM TECHNOLOGY CO., LTD. (BEIJING)
    Inventors: Hui Zhu, Meina Lin, Xiaomeng Chen, Zhen'gang Zhu, Xuan Zhao
  • Patent number: 10453889
    Abstract: A device includes two BSI image sensor elements and a third element. The third element is bonded in between the two BSI image sensor elements using element level stacking methods. Each of the BSI image sensor elements includes a substrate and a metal stack disposed over a first side of the substrate. The substrate of the BSI image sensor element includes a photodiode region for accumulating an image charge in response to radiation incident upon a second side of the substrate. The third element also includes a substrate and a metal stack disposed over a first side of the substrate. The metal stacks of the two BSI image sensor elements and the third element are electrically coupled.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: October 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen, Pin-Nan Tseng
  • Publication number: 20190318471
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: August 29, 2018
    Publication date: October 17, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 10417954
    Abstract: Provided is a display panel, including a plurality of gate lines extending in a row direction and arranged in a column direction; a plurality of data lines extending in a column direction and arranged in a row direction; a plurality of pixel units arranged in an array of M rows by N columns defined by the plurality of gate lines and the plurality of data lines intersecting each other; a first gate driver connected to pixel units from a first row to a mth row; and a second gate driver connected to pixel units from a (m+1)th row to a Mth row, where pixel units from the first row to the mth row of the nth column are connected to an integrated circuit through one of the plurality of data lines and pixel units from the (m+1)th row to the Mth row of the nth column are connected to the integrated circuit through another one of the plurality of data lines, where M, N, m and n are positive integers satisfying the following conditions: 1<m<M and 1<n<N. Split-screen display is made possible.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Xiamen Tianma Micro-Electronics Co., Ltd.
    Inventors: Kangpeng Yang, Yumin Xu, Chao Zheng, Shaofan Liu, Xiaomeng Chen
  • Publication number: 20190252389
    Abstract: A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Inventors: Chern-Yow HSU, Chen-Jong WANG, Chia-Shiung TSAI, Shih-Chang LIU, Xiaomeng CHEN
  • Publication number: 20190155164
    Abstract: A defect inspection method and a defect inspection system are provided. In the method, a plurality of candidate defect images are retrieved from inspection images obtained by at least one optical inspection tool performing hot scans on at least one wafer and a plurality of attributes are extracted from the inspection images. A random forest classifier including a plurality of decision trees for classifying the candidate defect images is created, wherein the decision trees are built with different subset of the attributes and the candidate defect images. A plurality of candidate defect images are retrieved from the optical inspection tool in runtime and applied to the decision trees, and classified into nuisance images and real defect images according to votes of the decision trees in which the nuisance images are filtered out. The real defect images with the votes over a confidence value are sampled for microscopic review.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Huei Chen, Hung-Yi Chung, Chao-Ting Hong, Cheng-Kuang Lee, Xiaomeng Chen, Teng-Cheng Hsu
  • Patent number: 10283448
    Abstract: A method of fabricating a semiconductor device includes providing a first substrate comprising a first conductive element exposed at a surface of the first substrate; forming a patterned photoresist layer atop the first conductive element, whereby the patterned photoresist layer provides openings exposing the first conductive element; forming a first metal layer in the openings and directly atop the first conductive element; forming a first insulator layer over the first metal layer and the first substrate; and polishing the first metal layer and the first insulator layer, resulting in a first interface surface over the first substrate wherein the first interface surface includes part of the first metal layer and the first insulator layer.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 7, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ping-Yin Liu, Kai-Wen Cheng, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai, Xiaomeng Chen