Abstract: Semiconductor devices having a direct backside contact are provided. In one aspect, a semiconductor device includes: at least one FET on a frontside of a wafer, where the wafer includes a semiconductor layer, and where a most backside-facing surface of the semiconductor layer is planar; and a backside contact disposed on the most backside-facing surface of the semiconductor layer, where the backside contact directly contacts source/drain regions of the at least one FET. A local wiring layer can be disposed on a most backside-facing surface of the backside contact. A method of fabricating the present semiconductor devices is also provided.

Abstract: A semiconductor device includes a substrate having a frontside, a backside, and a transistor that includes a gate region, a first source/drain region of a first depth into the substrate, and a second source/drain region of a second depth into the substrate. The semiconductor device further includes a backside contact (BC) region extending from the backside into the substrate and electrically connected to the first source/drain region. The semiconductor device further includes a backside partial diffusion break (BPDB) region that includes a non-conducting material, extending from the backside into the substrate and distinct from the first source/drain region.

Abstract: A semiconductor structure includes a substrate; a spacer protruding from the substrate and surrounding a cavity; and spin-on glass filling a portion of the cavity.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor; a power rail via between the first and the second transistor; a backside via below the power rail via, the backside via having a first portion directly contacting the power rail via and a second portion underneath the first portion; and an isolation spacer surrounding the second portion of the backside via. The backside via further includes a third portion underneath the second portion. A backside capping layer underneath the isolation spacer surrounds the third portion of the backside via. A method of forming the same is also provided.

Abstract: A semiconductor device is provided in which a frontside power via structure is in contact with a backside contact via structure that contains dual backside via liners present thereon. Notably, an inner backside via dielectric liner is located on a sidewall of the backside contact via structure, and an outer backside via dielectric liner is located on a sidewall of the inner backside via dielectric liner and on a topmost surface of the backside contact via structure.

Abstract: Embodiments relate to backside contact and backside isolation. An aspect includes a semiconductor structure having channel regions connected to a first source/drain region and a second source/drain region and a backside contact disposed under the first source/drain region. An aspect includes a liner vertically extending from a backside of the second source/drain region, the liner protecting the backside of the second source/drain region from contact with the backside contact.

Abstract: A microelectronic structure that includes a nanosheet FET located on a substrate where the nanosheet FET includes a source/drain. A frontside source/drain contact located on a frontside surface of the source/drain. A deep via located adjacent to the frontside source/drain contact, where the frontside source/drain contact is connected to the deep via. The deep via extends downwards to a backside region of the nanosheet FET. A deep via extension is located on a backside surface of the deep via, where the deep via extension is wider than the backside surface of the deep via.

Abstract: Methods of forming metal traces and a semiconductor structure are presented. The semiconductor structure comprises a substrate, a cutting pattern formed of hard masks protruding from the substrate, and photoresist positioned over the substrate such that openings in the photoresist direct print trenches to be formed in dielectrics of the substrate and the cutting pattern blocks portions of the openings to form tip-to-tip cuts in the trenches.

Abstract: Methods for full hard mask removal and a semiconductor structure are presented. A semiconductor structure comprises a base layer of dielectric material; a body layer of a low-k dielectric material over the base layer; a hard mask over the body layer; and a plurality of trenches etched through the hard mask and the body layer and only partially etched into the base layer.

Abstract: Semiconductor devices include stacked nanosheet channels with inner spacers between respective pairs of the stacked nanosheet channels. Dummy nanosheet remnants are below respective inner spacers, vertically aligned with the respective inner spacers. A source/drain structure is on sidewalls of the plurality of stacked nanosheet channels. A backside contact makes contact with the source/drain structure.

Abstract: Semiconductor devices are provided that include a conductor structure located in a shallow trench isolation structure that is positioned between two field effect transistors of a same conductivity type. The conductor structure is electrically connected to a backside contact structure, and the backside contact structure is electrically connected to at least one well region that straddles a sidewall of the backside contact structure. The area of contact between the backside contact structure and the well region provides a local well tap to the semiconductor device.

Abstract: A semiconductor device is provided including a backside deep trench capacitor present in a deep trench device region and electrically connected to a source/drain region of a transistor and to a backside back-end-of-the-line (BEOL) structure. In some embodiments, the semiconductor device can also include a logic device region including at least one logic transistor that is located adjacent to the deep trench device region.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first doped region under the STI, an N-well region connected to the first doped region and the STI on a first side, a P-well region connected to the first doped region and the STI on a second side, a backside contact. A dopant concentration of the first doped region is higher than the dopant concentration of the N-well region and the dopant concentration of the P-well region.

Abstract: The present application discloses a solar cell and a photovoltaic module, and relates to the field of photovoltaic technologies. As an example, a solar cell includes a semiconductor substrate, a first doped semiconductor portion, a first anti-reflection layer, and a second anti-reflection layer. The semiconductor substrate has a first surface having a first region and a second region that do not overlap. The first doped semiconductor portion is arranged on the first region. The first anti-reflection layer is arranged on a surface of the first doped semiconductor portion. The second anti-reflection layer is arranged on the second region. A difference between a surface reflectivity of a side of the first anti-reflection layer facing away from the semiconductor substrate and a surface reflectivity of a side of the second anti-reflection layer facing away from the semiconductor substrate is greater than or equal to 0.5% and less than or equal to 40%.

Abstract: A semiconductor device includes a logic device including a first portion of a first substrate extending vertically below a first source/drain region, a second portion of the first substrate extending vertically below a second source/drain region, a first shallow trench isolation (STI) extending vertically and isolating the first portion of the first substrate and the second portion of the first substrate, a backside power delivery network (BSPDN) below the logic device, a first dielectric layer extending vertically through sidewalls of a backside contact. The first dielectric layer isolates the backside contact from the first portion of the first substrate and the second portion of the first substrate.

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second transistor; a power rail via between the first and the second transistor; and a backside via below the power rail via and below the first and the second transistor, where the backside via has a first portion directly contacting the power rail via and a second portion around the first portion, and a top surface of the first portion is above a top surface of the second portion. A method of forming the same is also provided.

Abstract: A semiconductor device includes a shallow trench isolation (STI), a first well region connected to the insulating region and the STI on a first side, a second well region connected to the insulating region and the STI on a second side, and a backside contact including an upper portion, a lower portion, and a middle portion connecting the upper portion and the lower portion. A shape and a profile of the insulating region is same as a shape and a profile of the middle portion.