Abstract: Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops.

Abstract: Embodiments of the invention provide various methods for detecting a spatial division multiple access (SDMA) channel swap. A first SDMA communication channel is assigned to a first user terminal that initially transmits its signal over the first SDMA communication channel. A second SDMA communication channel is assigned to a second user terminal that initially transmits its signal over the second SDMA communication channel. The first user terminal's signal and the second user terminal's signal are analyzed to determine that the first user terminal is transmitting its signal over the second SDMA communication channel and the second user terminal is transmitting its signal over the first SDMA communication channel.

Abstract: A receiving device receives a stream of information and appended thereto a cyclic redundancy check (CRC) value for the information stream. A new CRC value is computed for the information stream and compared to the CRC value. If the CRC value and the new CRC value differ, then a segment of the information stream is altered, and a pointer based on the altered information stream is obtained. The pointer points to a table from which a value is obtained that is used in revising the new CRC value. The CRC value is compared to the new CRC value as revised, and if they still differ, again the information stream is altered, the new CRC value revised in connection therewith, and the CRC value again compared to the new CRC as revised. This process repeats until such time as any data integrity error in the information stream is corrected, or some other appropriate action is taken to end the process.

Abstract: An embodiment of the invention provides a method for effecting switchback on a spatial division multiple access (SDMA) PHS channel. A communication signal is broadcast over each of one or more SDMA channels of a multi-access channel to one or more corresponding user terminals. A set of transmit spatial weights is determined for a synchronization burst to a user terminal attempting to reestablish communication over an SDMA channel of the multi-access channel. The set of transmit spatial weights is determined such that interference caused by one or more communication signals to the synchronization burst is reduced.

Abstract: Embodiments of the invention provide various methods for detecting a spatial division multiple access (SDMA) channel swap. A first SDMA communication channel is assigned to a first user terminal that initially transmits its signal over the first SDMA communication channel. A second SDMA communication channel is assigned to a second user terminal that initially transmits its signal over the second SDMA communication channel. The first user terminal's signal and the second user terminal's signal are analyzed to determine that the first user terminal is transmitting its signal over the second SDMA communication channel and the second user terminal is transmitting its signal over the first SDMA communication channel.

Abstract: A footwear sole include a rubber inner sole and a textile outer sole. The textile outer sole is at least partially impregnated into at least one surface of the inner sole. A method of forming a footwear sole includes the steps of forming at least one inner sole and at least partially impregnating a textile material into at least a portion of at least one surface of the inner sole.

Abstract: Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines.

Abstract: A footwear sole include a rubber inner sole and a textile outer sole. The textile outer sole is at least partially impregnated into at least one surface of the inner sole. A method of forming a footwear sole includes the steps of forming at least one inner sole and at least partially impregnating a textile material into at least a portion of at least one surface of the inner sole.

Abstract: Techniques for testing a sequential circuit comprising a plurality of flip-flops or other types of registers. The circuit is first configured such that substantially all feedback loops associated with the registers, other than one or more self-loops each associated with a corresponding one of the registers, are broken. Test patterns are then generated for application to the circuit. The test patterns are applied to the circuit in conjunction with partitioned clock signals each of which is associated with a corresponding level of the circuit containing at least one of the self-loops. In an illustrative embodiment, a design for testability (DFT) structure is used to provide partitioning of a master clock into multiple clock signals each associated with a corresponding one of the levels of self-loops, so as to permit breaking of the feedback loops other than the self-loops.

Abstract: Test pattern generation is performed for a sequential circuit by first separating the circuit into overlapping pipelines by controlling corresponding clocks for one or more registers of the circuit so as to break feedback loops of the circuit, and then processing each of the pipelines separately in order to determine if particular target faults are detectable in the pipelines. Independent clocks may be provided for each of a number of registers of the circuit in order to facilitate the breaking of the feedback loops. The processing of the pipelines may include a first processing operation which detects target faults in a single time frame, and a second processing operation which detects target faults in two or more time frames. The first processing operation generates as many combinational test vectors as possible for each of the pipelines, while the second processing operation generates sequences of two or more combinational test vectors for each of the pipelines.