Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

Abstract: The invention discloses a biological desulfurizer for removing organic sulfur in fracturing flowback fluid and application thereof. The biological desulfurizer includes a compound with a triazine structure formed by modifying chitosan with aldehydes and inorganic salts. The triazine structure has a good removal effect on hydrogen sulfide and organic sulfur such as mercaptan and sulfide. The biological desulfurizer of the invention has a sulfur capacity of up to 250 g/kg and a desulfurization efficiency of over 95% in 15 min. It can effectively remove the stink of sulfur-containing working water, improve the working environment of the well site, and reduce the impact of sulfur compounds on the atmospheric environment during the development of oil and gas fields.

Abstract: A catalyst for producing dibasic amine by hydrogenation of dibasic nitrile contains the following components or reaction product thereof: a) an active component, wherein the active component comprises Ni and/or an oxide thereof; b) an auxiliary, wherein the auxiliary comprises one or more of Mg, Cu, Co, Zn, Zr, Mo and/or oxides thereof; C) support, wherein the relative content of ?-NiO in the catalyst is less than 2.0 a.u. A process for producing dibasic amine by hydrogenation of dibasic nitrile is also provided.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: A photodarkening-resistant ytterbium-doped quartz optical fiber and a method for prpearing such a fiber are provided. Glass of a photodarkening-resistant ytterbium-doped quartz optical fiber core rod includes at least Yb2O3, Al2O3, P2O5, SiO2. The proportions of Yb2O3, Al2O3, and P2O5 in the entire substance are Yb2O3: 0.05-0.3 mol %, Al2O3: 1-3 mol %, and P2O5: 1-5 mol %, respectively. In the preparation method for the photodarkening-resistant ytterbium-doped quartz optical fiber, a sol-gel method and an improved chemical vapor deposition method are combined. By using the molecular-level doping uniformity and the low preparation loss thereof respectively, ytterbium ions, aluminum ions and phosphorus ions are effectively doped in a quartz matrix, thereby effectively solving the problems in the optical fiber of high loss, photodarkening caused by cluster or the like, and a central refractive index dip.

Abstract: In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.

Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.

Abstract: According to one implementation of the present disclosure, a method includes fabricating a memory macro unit; forming a through silicon via (TSV); and bonding the TSV at least partially through the fabricated memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

Abstract: A method and system for analyzing a seismically active field based on expansion of an empirical orthogonal function is provided. The research region of the seismic active field is gridded at equal intervals for the preset research region of a seismic active field; a seismic active field function matrix correlated with the research region of the seismic active field spatially and temporally is constructed according to the gridding of the research region of the seismic active field; and the seismic active field function matrix is expanded with an empirical orthogonal function to obtain a main typical field and a temporal factor thereof, and an anomaly on the temporal factor of the seismic active field is analyzed with a method index, a parameter index and an anomaly index.

Abstract: According to one implementation of the present disclosure, an integrated circuit includes a memory macro unit, and one or more through silicon vias (TSVs) at least partially coupled through the memory macro unit. According to one implementation of the present disclosure, a computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to perform operations including: receiving a user input corresponding to dimensions of respective pitches of one or more through silicon vias (TSVs); determining whether dimensions of a memory macro unit is greater than a size threshold, wherein the size threshold corresponds to the received user input; and determining one or more through silicon via (TSV) positionings based on the determined dimensions of the memory macro unit.

Abstract: A radiation-resistant laser optical fiber preform core rod at least includes one type of activated ion (Yb3+, Er3+) and one or more types of co-doped ion (Al3+, P5+, Ge4+, Ce3+, F?), and —OD group of 16-118 ppm. Irradiation resistance of core rod glass can be effectively improved by sequentially performing pre-treatments, i.e. deuterium loading, pre-irradiation and thermal annealing on a preform core rod. Electron paramagnetic resonance test shows that, under the same radiation condition, the radiation induced color center concentration in a preform core rod treated by the method above is lower than in an untreated core rod by one or more orders of magnitude. The obtained core rod can be used for preparing a radiation-resistant rare earth-doped silica fiber, and has the advantages of high laser slope efficiency, low background loss, being able to be used stably in a vacuum environment for a long time, for example.

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first semiconductor device tier that includes first semiconductor devices. A first signal wiring structure can be formed over and electrically connected to the first semiconductor device tier. An insulator layer can be formed over the first signal wiring structure. A second semiconductor device tier can be formed over the insulator layer, the second semiconductor device tier including second semiconductor devices. A second signal wiring structure can be formed over and electrically connected to the second semiconductor device tier. An inter-tier via can be formed vertically through the insulator layer and electrically connecting the second signal wiring structure to the first signal wiring structure. The first semiconductor device tier, the second semiconductor device tier and the inter-tier via can be formed monolithically.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a first power delivery network (PDN) structure, and a first semiconductor device tier disposed over and electrically connected to the first PDN structure. The multi-tier semiconductor structure can further include a signal wiring tier disposed over and electrically connected to the first semiconductor device tier, a second semiconductor device tier disposed over and electrically connected to the signal wiring tier, and a second PDN structure disposed over and electrically connected to the second semiconductor device tier. The multi-tier semiconductor structure can further include a through-silicon via (TSV) structure electrically connected to the signal wiring tier, wherein the TSV structure penetrates the second PDN structure.

Abstract: A semiconductor device includes a first pair of transistors over a substrate. The first pair of transistors includes a first transistor having a first gate structure over the substrate and a second transistor having a second gate structure stacked over the first transistor. A second pair of transistors is stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate. The second pair of transistors includes a third transistor having a third gate structure stacked over the second transistor and a fourth transistor having a fourth gate structure stacked over the third transistor. The third gate structure extends from a central region of the vertical stack to a first side of the vertical stack. The second gate structure and the fourth gate structure extend from the central region to a second side of the vertical stack opposite the first side.

Abstract: Aspects of the present disclosure provide a multi-tier semiconductor structure. For example, the multi-tier semiconductor structure can include a lower semiconductor device tier, and a lower signal wiring structure electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include a primary power delivery network (PDN) structure disposed over the lower semiconductor device tier and the lower signal wiring structure and electrically connected to the lower semiconductor device tier. The multi-tier semiconductor structure can further include an upper semiconductor device tier disposed over and electrically connected the first PDN structure, and an upper signal wiring structure disposed over the primary PDN structure and electrically connected to the upper semiconductor device tier.

Abstract: An integrated circuit includes a first circuit and a power meter coupled to the first circuit at selected proxy locations. The power meter includes circuitry for generating toggle data, such as signal transitions or signal levels, from signals at the proxy locations and combiner circuitry for combining the toggle data in a first time window with a set of weight value to produce a measure of power usage in the first circuit. The proxy locations and weight values are selected automatically based on simulated or emulated signals from a larger set of locations in the first circuit and associated power usage in the first circuit.

Abstract: According to one implementation of the present disclosure, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing respective inter-tier connections coupling for first and second networks concurrently on the generated 3D circuit design. The first networks may include power or ground networks, while the second networks may include signal networks. In another implementation, a method includes: generating a three-dimensional (3D) circuit design of an integrated circuit; and providing inter-tier connections on the generated 3D circuit design during one of a placement stage, a partitioning stage, a clock tree synthesis (CTS) stage, or a routing stage of a physical circuit design procedure.