Abstract: A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) throug

Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment.

Abstract: A method for preparing a power diode, including: providing a substrate (10), growing a N type layer (20) on the front surface of the substrate (10); forming a terminal protecting ring; forming an oxide layer (30), knot-pushing to the terminal protecting ring; forming a gate oxide layer (60), depositing a poly-silicon layer (70) on the gate oxide layer (60); depositing a SiO2 layer (80) on the surface of the poly-silicon layer (70) and a oxide layer (50); forming a N type heavy doped region (92); forming a P+ region; removing a photoresist, implanting P type ions using the SiO2 layer (80) as a mask layer, and forming a P type body region; heat annealing; forming a side wall structure in the opening of the poly-silicon layer (70), the gate oxide layer (60) being etched, and removing the SiO2 layer (80); and processing a front surface metallization and a back surface metallization treatment.

Abstract: A preparation method for a power diode, comprising: providing a substrate (10), the substrate (10) having a front surface and a back surface opposite to the front surface, an N-type layer (20) growing on the front surface of the substrate (10), and the N-type layer (20) having a first surface deviating from the substrate (10); forming a terminal protection ring (31, 32, 33); forming an oxide layer (50), and performing knot pushing on the terminal protection ring (31, 32, 33); conducting photoetching using a photoetching plate of an active region and etching the oxidation layer (50) of the active region, and forming a gate oxide layer (60) on the first surface of the N-type layer (20) of the active region; depositing on the gate oxide layer (60) to form a polysilicon layer (70); conducting photoetching using a polysilicon photoetching plate, taking a photoresist (40) as a mask layer to inject P-type ions into the N-type layer (20), and forming a P-type body region (82) beneath the polysilicon layer (70) throug

Abstract: An insulated gate bipolar transistor (100) is provided. A substrate (10) of the insulated gate bipolar transistor (100) is of an N type. A P-type region (16) is disposed on a back of the N-type substrate. A back metal structure (18) is disposed on a back of the P-type region (16). A terminal protection ring is disposed in a terminal structure. A polysilicon gate (31) is disposed on a front surface of the substrate (10) in an active region. Sidewalls (72) are disposed at two sides of the polysilicon gate (31) on the substrate (10). An interlayer medium (81) covered with the polysilicon gate (31) and the sidewalls (72) is disposed on the substrate (10). The interlayer medium (81) is covered with a metal lead wire layer (91). An N-type carrier enhancement region (41) is disposed in the substrate (10) in the active region. A P-type body region (51) is disposed in the carrier enhancement region (41). An N-type heavily doped region (61) is disposed in the P-type body region (51).

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract: An insulated gate bipolar translator (IGBT) with a built-in diode and a manufacturing method thereof are provided.

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method thereof. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer (1) departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure (10) is provided with a back-surface metal layer (12). A plurality of polysilicon filling structures (11) which penetrate into the electric field stop layer (1) from the back-surface P-type structure (10) are formed in the active region (100).

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

Abstract: Disclosed is a method for removing a polysilicon protection layer (12) on a back face of an IGBT having a field stop structure (10). The method comprises thermally oxidizing the polysilicon protection layer (12) on the back face of the IGBT until the oxidation is terminated on a gate oxide layer (11) located above the polysilicon protection layer (12) to form a silicon dioxide layer (13), and removing the formed silicon dioxide layer (13) and the gate oxide layer (11) by a dry etching process. The method for removing the protection layer is easier to control.