Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. A corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: A data-dependent noise predictive (DDNP) adaptation module operable to support Viterbi branch metric calculations within a hard disk drive (HDD) controller is provided. This DDNP adaptation module includes a DDNP filter tap coefficient adaptation module, a DDNP filter gain scaling module, and a DDNP bias compensation module. The combination of the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module is operable to receive an error signal and a NRZ pattern and produce tap coefficients. A whitened error signal calculation module coupled to the DDNP filter tap coefficient adaptation module, the DDNP filter gain scaling module, and the DDNP bias compensation module, the whitened error signal calculation module operable to calculate a whitened error signal based on the error signal, NRZ pattern, and tap coefficients. This whitened error signal is used to support the Viterbi branch metric calculations.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and precoding the encoded information. The precoding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: An interleaver employs a generalized method of generating a mapping. The mapping is generated for interleaving bits of a data block and associated error detection/correction information. The data block is of length N, and the length of the error detection/correction information is P. An (N+P)×(N+P) square matrix is formed and divided into sub-blocks, where one portion of the matrix is associated with error detection/correction information and another portion is associated with data of the data block. New positions in the matrix are generated in a time sequence on a sub-block by sub-block basis based on a generator seed pair and an original position seed pair. The time sequence also corresponds to positions in an output interleaved block. Once the new position sequence is generated, the matrix is populated with data and error detection/correction information based on the corresponding time sequence. A de-interleaver performs the inverse mapping of the interleaver.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). In one embodiment, an encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. A corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The precoding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.