Abstract: A semiconductor device includes at least one RF power amplifier (RFPA) and a voltage supply adjustment network coupled with the RFPA for providing an internal supply voltage to the RFPA based on an applied input voltage. The voltage supply adjustment network includes multiple resistors, multiple Zener diodes, a voltage return connection, an internal supply voltage connection coupled with the RFPA for conveying the supply voltage to the RFPA, an input voltage connection adapted to receive the input voltage, and a configurable connection network coupled with the resistors and Zener diodes. A subset of the resistors and Zener diodes are selectively connected together between the input voltage and the voltage return connections via corresponding conductive links to provide a prescribed output voltage to the internal supply voltage connection as a function of the applied input voltage. The connection network is configured by applying an energy source to a selected conductive link(s) in the connection network.

Abstract: A semiconductor device includes at least one RF power amplifier (RFPA) and a voltage supply adjustment network coupled with the RFPA for providing an internal supply voltage to the RFPA based on an applied input voltage. The voltage supply adjustment network includes multiple resistors, multiple Zener diodes, a voltage return connection, an internal supply voltage connection coupled with the RFPA for conveying the supply voltage to the RFPA, an input voltage connection adapted to receive the input voltage, and a configurable connection network coupled with the resistors and Zener diodes. A subset of the resistors and Zener diodes are selectively connected together between the input voltage and the voltage return connections via corresponding conductive links to provide a prescribed output voltage to the internal supply voltage connection as a function of the applied input voltage. The connection network is configured by applying an energy source to a selected conductive link(s) in the connection network.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: In the subject system for polarity detection, link initialization between a primary device and a secondary device may be performed in at least two stages, a half-duplex stage when only the primary device transmits initialization signals and any encoded handshaking signals may be set to false, and a full-duplex stage when both devices may transmit initialization signals. The secondary device may perform polarity detection during the half-duplex stage. If the secondary device determines that the polarities of the received signals are reversed, the secondary device may reverse the polarities of any signals subsequently received from, and transmitted to, the primary device. In this manner, the polarities can be corrected for both devices during the half-duplex stage by the secondary device. The secondary device may initiate the full-duplex link initialization stage, during which any handshaking signals may be exchanged, by transmitting signals to the primary device.

Abstract: An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value.

Abstract: In some aspects, the disclosure is directed to methods and systems for a device including a physical interface with electrical connection to a communication channel, and circuitry configured to detect energy received at the physical interface, wait a predetermined length of a time until the beginning of a time slot, monitor the physical interface during the time slot for a predefined pattern from the communication channel, and upon detection of the predefined pattern, transition the device to an increased-power mode.

Abstract: In the subject system for polarity detection, link initialization between a primary device and a secondary device may be performed in at least two stages, a half-duplex stage when only the primary device transmits initialization signals and any encoded handshaking signals may be set to false, and a full-duplex stage when both devices may transmit initialization signals. The secondary device may perform polarity detection during the half-duplex stage. If the secondary device determines that the polarities of the received signals are reversed, the secondary device may reverse the polarities of any signals subsequently received from, and transmitted to, the primary device. In this manner, the polarities can be corrected for both devices during the half-duplex stage by the secondary device. The secondary device may initiate the full-duplex link initialization stage, during which any handshaking signals may be exchanged, by transmitting signals to the primary device.

Abstract: A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: Aspects of a method and system for physical-layer handshaking for timing role transition are provided. Prior to changing the timing role of a first Ethernet device, the first Ethernet device may communicate over an Ethernet link to a second Ethernet PHY utilizing a first set of one or more PCS code-groups. In response to a determination to change the timing role of the first Ethernet device, the first Ethernet device may communicate one or more IDLE symbols over the Ethernet link to the second Ethernet device. The IDLE symbol(s) may be generated utilizing a second set of one or more PCS code-groups. The first set of PCS code-group(s) may be mutually exclusive with the second set of PCS code-group(s). In response to detecting a received Ethernet physical layer symbol corresponding to the second set of PCS code-groups, the second Ethernet device may make a determination to change its timing role.

Abstract: An Ethernet PHY may receive an indication from a local timing source that a local clock is suitable for propagation to a link partner. In response, a timer in the Ethernet PHY may be started. In instances that the Ethernet PHY receives, during a time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, the Ethernet PHY may be configured as timing slave. In instances that the Ethernet PHY does not receive, during the time period subsequent to starting the timer and before the timer reaches a predetermined value, an indication that the link partner is propagating a clock that is suitable for the Ethernet PHY to synchronize to, Ethernet PHY may be configured as timing master upon the timer reaching the predetermined value.

Abstract: A first PHY may be coupled to a second PHY via a network link. The first PHY may transition from a role of timing master for the network link to a role of timing slave for the network link. During a first time interval subsequent to the transition, the PHYs may communicate half-duplex over the link while the first PHY synchronizes to a transmit clock of the second PHY. During a second time interval, the PHYs may communicate full-duplex while the second Ethernet PHY synchronizes to a transmit clock of the first PHY. Also during the second time interval, the first PHY may determine that the first PHY and the second PHY are synchronized. Subsequent to the determination, the PHYs may begin full-duplex communication of data on the network link.

Abstract: Embodiments of the present invention enable robust and quick parallel detection of the remote LPI request signal (rem_lpi_req) and SEND ZERO mode (SEND_Z) defined in the Energy Efficient Ethernet (EEE) standard. Embodiments do not rely on energy detection for detecting SEND_Z. Therefore, SEND_Z can be detected reliably and with minimal latency. In addition, since SEND_Z and rem_lpi_req are detected in parallel, embodiments are not concerned with the false detection of rem_lpi_req (before SEND_Z is detected) or the need to disable detection of rem_lpi_req (after SEND_Z is detected).

Abstract: Embodiments of the present invention enable robust and quick parallel detection of the remote LPI request signal (rem_lpi_req) and SEND ZERO mode (SEND_Z) defined in the Energy Efficient Ethernet (EEE) standard. Embodiments do not rely on energy detection for detecting SEND_Z. Therefore, SEND_Z can be detected reliably and with minimal latency. In addition, since SEND_Z and rem_lpi_req are detected in parallel, embodiments are not concerned with the false detection of rem_lpi_req (before SEND_Z is detected) or the need to disable detection of rem_lpi_req (after SEND_Z is detected).

Abstract: A technique to perform a guided partial response target search for characterizing a read channel of a disk drive. A target adaptation scheme pre-selects a plurality of targets from a pool of potential targets based on certain criteria and the selected targets are sorted in linear gradient orders. When target adaptation is being performed by comparing the equalizer output with an ideal reconstructed signal, a difference value sets a gradient vector that is used to determine which direction to move along the sorted list of targets to select the next target.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and preceding the encoded information. The preceding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: An interleaver employs a generalized method of generating a mapping. The mapping is generated for interleaving bits of a data block and associated error detection/correction information. The data block is of length N, and the length of the error detection/correction information is P. An (N+P)×(N+P) square matrix is formed and divided into sub-blocks, where one portion of the matrix is associated with error detection/correction information and another portion is associated with data of the data block. New positions in the matrix are generated in a time sequence on a sub-block by sub-block basis based on a generator seed pair and an original position seed pair. The time sequence also corresponds to positions in an output interleaved block. Once the new position sequence is generated, the matrix is populated with data and error detection/correction information based on the corresponding time sequence. A de-interleaver performs the inverse mapping of the interleaver.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.