Patents by Inventor Xiaoxin Zhang

Xiaoxin Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130027624
    Abstract: A TFT array substrate includes a pixel region and a wiring region disposed outside the pixel region. The wiring region has a wiring layer including scan or data wirings. A repair wiring layer including repair wiring is disposed insulatedly below or above the wiring layer. A scan or data wiring has a first intersection and a second intersection with a repair wiring section of the repair wiring. When the scan or data wiring is broken, a repair wiring section is cut off the repair wiring by a first cut-off point and a second cut-off point, and the broken scan or data wiring is electrically connected to the repair wiring section through soldering the first intersection and the second intersection. Thus, products that would otherwise be rejected in the manufacturing process of LCD panels can be repaired, which decreases the reject ratio, increases the yield and saves the production cost.
    Type: Application
    Filed: September 29, 2011
    Publication date: January 31, 2013
    Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.
    Inventors: Yizhuang Zhuang, Jungmao Tsai, Songxian Wen, Mingfeng Deng, Xiaoxin Zhang
  • Publication number: 20120134446
    Abstract: Modem coding and modulation techniques have greatly improved the transmission and reception of signals. A method is described including receiving a signal de-mapping the signal into a first and second substream, decoding the first and second substream using a low density parity check decoding process, and combining the first and second decoded substream into a single data stream. An apparatus is described including a symbol de-mapper that receives a signal de-maps the modulation symbols in the signal into a first and second substream, a first decoder that decodes the first substream using a low density parity check coding process at a first decoding rate, a second decoder that decodes the second substream at a second encoding rate, and a combiner that combines the first substream and the second substream into a single data stream.
    Type: Application
    Filed: July 20, 2010
    Publication date: May 31, 2012
    Inventors: Wei Zhou, Li Zou, Yuping Zhao, Xiaoxin Zhang, Peng Liu, Charles Chuanming Wang
  • Publication number: 20120134423
    Abstract: Modern coding and modulation techniques have greatly improved the transmission of signals. A method is described including receiving a stream of data bits, demultiplexing the stream into a first and second substream, encoding the first and second substream using a low density parity check coding process, and mapping the first substream to a first region of a symbol constellation map and the second substream to a second region. Also, an apparatus is described including a demultiplexer that produces a first and second bitstream, a first encoder that encodes the first substream using a low density parity check coding process at a first encoding rate, a second encoder that encodes the second substream at a second rate, and a symbol mapper that maps bits from the first substream to a first region of a symbol constellation map and maps bits from the second substream to a second region.
    Type: Application
    Filed: July 20, 2010
    Publication date: May 31, 2012
    Inventors: Wei Zhou, Li Zou, Yuping Zhao, Xiaoxin Zhang, Peng Liu, Charles Chuanming Wang
  • Publication number: 20120124523
    Abstract: The present disclosure discloses a method of displaying a cascading menu that includes a plurality of submenus. The method determines a first submenu as indicated for browsing by a user based on a clicking event of the user. When an operation interface of the first submenu is in a collapsed mode, a number of submenus that are currently in an expanded mode within an operation interface of the cascading menu is counted. When the number of submenus that are currently in the expanded mode reaches a defined threshold, at least a second submenu is selected from the submenus that are currently in the expanded mode, and an operation interface of the second submenu is shrunk. The operation interface of the first submenu is expanded. Therefore, a size of the operation interface of the cascading menu will not increase as the number of the expanded submenus increases. As such, the amount of a page space occupied by the cascading menu is reduced and utilization of the page space is improved.
    Type: Application
    Filed: April 29, 2010
    Publication date: May 17, 2012
    Applicant: ALIBABA GROUP HOLDING LIMITED
    Inventors: Xiaoxin Zhang, Changyuan Yang
  • Publication number: 20120115966
    Abstract: The present invention provides a process for preparing methanol, dimethyl ether, and low carbon olefins from syngas, wherein the process comprises the step of contacting syngas with a catalyst under the conditions for converting the syngas into methanol, dimethyl ether, and low carbon olefins, characterized in that, the catalyst contains an amorphous alloy consisting of a first component Al and a second component, said second component being one or more elements or oxides thereof selected from Group IA, IIIA, IVA, VA, IB, IIB, IVB, VB, VIIB, VIIB, VIII, and Lanthanide series of the Periodic Table of Elements, and said second component being different from the first component Al. According to the present process, the syngas can be converted into methanol, dimethyl ether, and low carbon olefins in a high CO conversion, a high selectivity of the target product, and high carbon availability.
    Type: Application
    Filed: November 26, 2009
    Publication date: May 10, 2012
    Applicants: Research Institute of Petroleum Processing, SINOPEC, China Petroleum & Chemical Corporation
    Inventors: Qiang Fu, Xiaoxin Zhang, Yibin Luo, Xuhong Mu, Baoning Zong
  • Publication number: 20120083539
    Abstract: The present invention provides a process for preparing methanol, dimethyl ether, and low carbon olefins from syngas, wherein the process comprises the step of contacting syngas with a catalyst under the conditions for converting the syngas into methanol, dimethyl ether, and low carbon olefins, characterized in that, the catalyst contains an amorphous alloy consisting of components M and X wherein the component X represents an element B and/or P, the component M represents two or more elements selected from Group IIIA, IVA, VA, IB, IIB, IVB, VB, VIB, VIIB, VIII and Lanthanide series of the Periodic Table of Elements. According to the present process, the syngas can be converted into methanol, dimethyl ether, and low carbon olefins in a high CO conversion, a high selectivity of the target product, and high carbon availability.
    Type: Application
    Filed: December 15, 2009
    Publication date: April 5, 2012
    Applicants: Research Instutute of Petroleum Procesing, Sinopec, China Petroleum & Chemical Corporation
    Inventors: Qiang Fu, Xiaoxin Zhang, Yibin Luo, Xuhong Mu, Baoning Zong
  • Patent number: 8022408
    Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
  • Patent number: 8012819
    Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: September 6, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiaoxin Zhang, Wenxu Xianyu, Takashi Noguchi, Hans S. Cho, Huaxiang Yin
  • Publication number: 20110078533
    Abstract: A concatenated coded modulation communication system and method combines Trellis Coded Modulation with non-Gray code constellation mapping, interleaving, and non-binary Low Density Parity Check coded channel modulation with Gray code constellation mapping to improve error performance.
    Type: Application
    Filed: June 24, 2009
    Publication date: March 31, 2011
    Inventors: Wei Zhou, Li Zou, Yuping Zhao, Xiaoxin Zhang
  • Publication number: 20100200834
    Abstract: Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
    Type: Application
    Filed: March 22, 2010
    Publication date: August 12, 2010
    Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
  • Patent number: 7772711
    Abstract: A semiconductor device including a substrate, a P-MOS single crystal TFT formed on the substrate, and an N-MOS single crystal TFT formed on the P-MOS single crystal TFT. The source region of the P-MOS single crystal TFT and the source region of the N-MOS single crystal TFT may be connected to each other. The P-MOS single crystal TFT and the N-MOS single crystal TFT may share a common gate. Also, the P-MOS single crystal TFT may include a single crystal silicon layer with a crystal plane of (100) and a crystal direction of <100>. The N-MOS single crystal TFT may include a single crystal silicon layer having the same crystal direction as the single crystal silicon layer of the P-MOS single crystal TFT and having a tensile stress greater than the single crystal silicon layer of the P-MOS single crystal TFT.
    Type: Grant
    Filed: May 9, 2006
    Date of Patent: August 10, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Noguchi, Hans S. Cho, Wenxu Xianyu, Do-young Kim, Jang-yeong Kwon, Huaxiang Yin, Kyung-bae Park, Xiaoxin Zhang
  • Patent number: 7714330
    Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: May 11, 2010
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Do-Young Kim, Huaxiang Yin, Xiaoxin Zhang
  • Publication number: 20100112763
    Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.
    Type: Application
    Filed: January 7, 2010
    Publication date: May 6, 2010
    Inventors: Xiaoxin Zhang, Wenxu Xianyu, Takashi Noguchi, Hans S. Cho, Huaxiang Yin
  • Publication number: 20100080327
    Abstract: A method for automatic gain control used in a receiver of a multi-carrier telecommunication system, the method comprising: receiving an input signal digitalized by an A/D converter; determining distribution of the input signal; and controlling gain of a variable gain amplifier as a function of the determined distribution.
    Type: Application
    Filed: December 25, 2006
    Publication date: April 1, 2010
    Inventors: Xiaoxin Zhang, Qiang Li, Yuping Zhao, Li Zou, Chuanming Wang
  • Patent number: 7667300
    Abstract: A semiconductor device includes a transistor. The transistor includes a substrate having an inclined surface, a first upper surface extending from a lower portion of the inclined surface, and a second upper surface extending from an upper end of the inclined surface. A gate stack structure is formed on the inclined surface and includes a gate electrode. A first impurity region formed on one of the first and second upper surfaces contacts the gate stack structure. A second impurity region formed on the second upper surface contacts the gate stack structure. A channel between the first and second impurity regions is formed along the inclined surface in a crystalline direction.
    Type: Grant
    Filed: November 17, 2006
    Date of Patent: February 23, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Xiaoxin Zhang, Wenxu Xianyu, Takashi Noguchi, Hans S. Cho, Huaxiang Yin
  • Publication number: 20100041214
    Abstract: A high quality single crystal substrate and a method of fabricating the same are provided. The method of fabricating a single crystal substrate includes: forming an insulator on a substrate; forming a window in the insulator, the window exposing a portion of the substrate; forming an epitaxial growth silicon or germanium seed layer on the portion of the substrate exposed through the window; depositing a silicon or germanium material layer, which are crystallization target material layers, on the epitaxial growth silicon 6r germanium seed layer and the insulator; and crystallizing the crystallization target material layer by melting and cooling the crystallization target material layer.
    Type: Application
    Filed: August 7, 2009
    Publication date: February 18, 2010
    Inventors: Hans S. Cho, Takashi Noguchi, Wenxu Xianyu, Xiaoxin Zhang, Huaxiang Yin
  • Patent number: 7662678
    Abstract: Provided are methods of forming a more highly-oriented silicon thin layer having a larger grain size, and a substrate having the same. The methods may include forming an aluminum (Al) layer on a base substrate, forming a more highly-oriented Al layer by recrystallizing the Al layer under vacuum, forming a more highly-oriented ?-Al2O3 layer on the more highly-oriented Al layer and/or epitaxially growing a silicon layer on the more highly-oriented ?-Al2O3 layer. The method may be used to manufacture a semiconductor device having higher carrier mobility.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: February 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Hans S. Cho, Takashi Noguchi, Young-Soo Park, Xiaoxin Zhang, Huaxiang Yin, Hyuck Lim, Kyung-Bae Park, Suk-Pil Kim
  • Patent number: 7566364
    Abstract: Provided may be a method of fabricating nanowires and a method of fabricating a transistor having the same. The method may include: forming a template layer on a substrate, the template layer having a first lateral surface and a second lateral surface facing the first surface; forming pores in the template layer, the pores disposed between the first lateral surface and the second lateral surface in the template layer and having first apertures in the first lateral surface; forming a single-crystalline material layer contacting the first apertures disposed in the first lateral surface of the template layer; forming second apertures connecting pores disposed in the second lateral surface; supplying gaseous crystal growth materials through the second apertures; and forming crystalline nanowires in the pores by crystal growth from the single-crystalline material layer. The nanowires may be made of crystalline materials, e.g., Si or SiGe, and may be formed parallel to the substrate.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: July 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wenxu Xianyu, Young-Soo Park, Takashi Noguchi, Hans S. Cho, Xiaoxin Zhang, Huaxiang Yin
  • Patent number: 7560317
    Abstract: Provided are a method of forming a single crystalline silicon layer, a structure including the same, and method of fabricating a thin film transistor (“TFT”) using the same. The method of forming the single crystalline silicon layer includes forming a silicon nitride layer on a substrate, forming an insulating layer on the silicon nitride layer, forming a hole in the insulating layer to a predetermined dimension, depositing a first silicon layer on an exposed bottom of the hole using a selective deposition process, depositing a second silicon layer on the insulating layer and the first silicon layer formed in the hole, and crystallizing the second silicon layer using a thermal process. In this method, a high-quality single crystalline silicon layer can be obtained.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: July 14, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Noguchi, Wenxu Xianyu, Xiaoxin Zhang, Hans S. Cho, Kyung-bae Park
  • Patent number: 7557411
    Abstract: Semiconductor-on-insulator (SOI) structures, semiconductor devices using the same and methods of manufacturing the same, and more particularly, to a structure with a single-crystalline (for example, germanium (x-Ge)) layer on an insulating layer, semiconductor devices using the same, and methods of manufacturing the same. The SOI structure may include a single-crystalline substrate formed of a first semiconductor material, a first insulating layer formed on the substrate and having at least one window exposing a portion of the substrate, a first epitaxial growth region formed on a surface of the substrate exposed by the window and formed of at least one of the first semiconductor material and a second semiconductor material, and a first single-crystalline layer formed on the first insulating layer and the first epitaxial growth region and formed of the second semiconductor material, and crystallized using a surface of the first epitaxial growth region as a seed layer for crystallization.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Takashi Noguchi, Hans S. Cho, Wenxu Xianyu, Huaxiang Yin, Xiaoxin Zhang