Abstract: The present invention provides an infrared pixel structure and a hybrid imaging device which use comb-shaped top plates and bottom plates to form capacitors. The upper electrode has a non-fixed end such that the infrared sensitive element in the upper electrode generates thermal stress and deforms when absorbing the infrared light, which changes the capacitance of the capacitors formed by the top plates and the bottom plates to achieve infrared detection and increase the device sensitivity. Furthermore, the infrared pixel structure can be used in an infrared light and visible light hybrid imaging device to achieve visible light imaging and infrared imaging in a same silicon substrate, so as to increase the imaging quality.

Abstract: The present invention provides an infrared detector pixel structure and manufacturing method thereof.

Abstract: The present invention provides an infrared detector pixel structure and manufacturing method thereof. The bottom portion of a silicon substrate is bonded with a bonding substrate, an infrared absorbing layer in the bonding substrate is used for absorbing a part of infrared light, a closed cavity filled with infrared-sensitive gas is set in the silicon substrate, and a piezoelectric transforming unit is bonded onto the closed cavity. When the infrared-sensitive gas absorbs the infrared light to expand, the infrared sensitive gas will press the piezoelectric transforming unit, which causes piezoelectric signal generated by the piezoelectric transforming unit to be changed, thereby achieving the detection on the infrared light.

Abstract: One variation of a method for tracking patient recovery during a physical therapy program includes: assigning a recovery plan to a patient, the recovery plan defining temporal quantitative targets for range of motion of a joint; during a first physical therapy session: prompting the patient to record a first digital photographic image of the joint in flexion; and prompting the patient to record a second digital photographic image of the joint in extension. The method also includes extracting an angular range of motion of the joint from the first digital photographic image and the second digital photographic image; in response to the angular range of motion of the joint deviating from the recovery plan by more than a threshold deviation, compiling the angular range of motion of the joint into a notification; and serving the notification to a computing device associated with a care provider.

Abstract: A capacitive silicon microphone comprises: a first dielectric layer sets on a substrate with a back cavity, a lower polar plate which is located over the back cavity, a first elastic member of which an inner edge is connected with the edge of the lower polar plate and an outer edge is located on the upper surface of the first dielectric layer, a second dielectric layer which is located on the outer edge of the first elastic member and right above the first dielectric layer, an upper polar plate which has a plurality of release holes and is formed above the lower polar plate with an air gap in between, a second elastic member of which an inner edge is connected with the edge of the upper polar plate and an outer edge is located on the upper surface of the second dielectric layer.

Abstract: A MEMS microphone structure, comprising a semiconductor substrate having a cavity, a first dielectric layer having a through-hole communicating with the cavity, a lower diaphragm electrode formed above the through-hole and at least partially attached to the upper surface of the first dielectric layer, and an upper electrode structure with an insulating layer. The upper electrode structure comprises an annular supporter, a back plate having multiple holes, and an upper electrode connection. At least a part of the annular supporter extends downwardly to the lower diaphragm electrode while the rest of the annular supporter extends downwardly to the substrate. The back plate is suspended above the lower diaphragm electrode by the annular supporter, forming an air gap therebetween. An upper electrode is embedded in the insulating layer at the back plate and is lead out by the upper electrode connection.

Abstract: A capacitive silicon microphone comprises: a first dielectric layer sets on a substrate with a back cavity, a lower polar plate which is located over the back cavity, a first elastic member of which an inner edge is connected with the edge of the lower polar plate and an outer edge is located on the upper surface of the first dielectric layer, a second dielectric layer which is located on the outer edge of the first elastic member and right above the first dielectric layer, an upper polar plate which has a plurality of release holes and is formed above the lower polar plate with an air gap in between, a second elastic member of which an inner edge is connected with the edge of the upper polar plate and an outer edge is located on the upper surface of the second dielectric layer.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

Abstract: A MEMS microphone structure, comprising a semiconductor substrate having a cavity, a first dielectric layer having a through-hole communicating with the cavity, a lower diaphragm electrode formed above the through-hole and at least partially attached to the upper surface of the first dielectric layer, and an upper electrode structure with an insulating layer. The upper electrode structure comprises an annular supporter, a back plate having multiple holes, and an upper electrode connection. At least a part of the annular supporter extends downwardly to the lower diaphragm electrode while the rest of the annular supporter extends downwardly to the substrate. The back plate is suspended above the lower diaphragm electrode by the annular supporter, forming an air gap therebetween. An upper electrode is embedded in the insulating layer at the back plate and is lead out by the upper electrode connection.

Abstract: The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.

Abstract: A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element (37) and a multi-layer structure of a standard CMOS device arranged on the silicon substrate (31). A deep groove (38) having a light-transmitting space therein is formed above the photosensitive element, a side wall of the deep groove is surrounded by a light reflection shielding layer (39) continuously arranged in a longitudinal direction to reflect the light incident on the light reflection shielding layer. The side wall of the deep groove is surrounded by metal interconnects, vias, contact holes and polysilicon in annular configurations, thus the incident light on the deep grove is substantially completely reflected, which avoids the optical crosstalk and effectively improves the optical resolution and sensitivity of the pixel and the performance and reliability of the chip.

Abstract: A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

Abstract: A pixel structure of a CMOS image sensor pixel structure and a manufacturing method thereof. The structure comprises a photosensitive element (37) and a multi-layer structure of a standard CMOS device arranged on the silicon substrate (31). A deep groove (38) having a light-transmitting space therein is formed above the photosensitive element, a side wall of the deep groove is surrounded by a light reflection shielding layer (39) continuously arranged in a longitudinal direction to reflect the light incident on the light reflection shielding layer. The side wall of the deep groove is surrounded by metal interconnects, vias, contact holes and polysilicon in annular configurations, thus the incident light on the deep grove is substantially completely reflected, which avoids the optical crosstalk and effectively improves the optical resolution and sensitivity of the pixel and the performance and reliability of the chip.

Abstract: The present disclosure relates to the use of telemedicine software and/or games to meet rehabilitation or physical training needs. More specifically, the disclosure relates to methods and systems that motivate and guide users in the course of a program which takes place at an institution, where the user initiates recovery or training, and/or at home, when the user must maintain a rehabilitation or physical training schedule to fully recover or complete training.

Abstract: A method is provided for manufacturing a semiconductor device with a metal film resistor structure. The method includes providing an insulation layer on the semiconductor device. A lower copper interconnect is formed in the insulation layer. The method also includes forming a cap layer on the insulation layer and the lower copper interconnect and etching the cap layer based on a single photolithography mask to form a window exposing portion of the lower copper interconnect and portion of the insulation layer. Further, the method includes forming a metal film layer on the cap layer and inside the window such that exposed portion of the lower copper interconnect is connected with part of the metal film layer within the window. The method also includes performing a chemical mechanical polishing (CMP) process to form a metal film resistor based on the metal film layer. The metal film resistor is connected with the portion of the lower copper interconnect.

Abstract: The present invention relates to an interconnection structure and a method for fabricating the same. According to the present invention, cavities are formed between the interconnection dielectric by using a sacrificial layer, carbon nanotubes are used as the interconnection material for local interconnection between via holes, graphene nanoribbons are used as the interconnection material for metal lines, and cavities are included in the interconnection dielectric. In addition, the conventional CMOS BEOL Cu interconnection technique is applied to the intermediate interconnection level and the global interconnection level. In this way, the high parasitic resistance and parasitic capacitance in the Cu interconnection technique, which may occur when the local interconnection is relatively small in size, can be effectively overcome.

Abstract: A method is disclosed for manufacturing a semiconductor device with a copper interconnect structure. The method includes providing a substrate, forming a first interconnect dielectric layer on the substrate, and forming a second interconnect dielectric layer on a surface of the first interconnect dielectric layer. The method also includes forming a plurality of conduits extending through the first interconnect dielectric layer and the second interconnect dielectric layer, and depositing copper in the plurality of conduits to form a copper interconnect layer of the copper interconnect structure. Further, the first interconnect dielectric layer, between neighboring conduits, contains cavities such that dielectric constant of the first interconnect dielectric layer is reduced. The second interconnect dielectric layer seals the top of the cavities, the substrate is the bottom of the cavities, and a width of the top of the cavities is less than a width of the bottom of the cavities.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.

Abstract: The invention is related to a MOS transistor and its fabrication method to reduce short-channel effects. Existing process has the problem of high complexity and high cost to reduce short-channel effects by using epitaxial technique to produce an elevated source and drain structure. In the invention, the MOS transistor, fabricated on a silicon substrate after an isolation module is finished, includes a gate stack, a gate sidewall spacer, and source and drain areas. The silicon substrate has a groove and the gate stack is formed in the groove.