Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: A liquid crystal writing screen, including: first substrate and second substrates, and a bistable liquid crystal layer between the first and second substrates, where the first substrate includes: a first base substrate; a plurality of pixel units on a side of the first base substrate proximate to the second substrate, each pixel unit including a thin film transistor, and a pixel electrode electrically connected to a first electrode of the thin film transistor; a passivation layer on a side of the thin film transistor distal from the first base substrate and in contact with the thin film transistor; where the pixel electrode is between the first base substrate and the passivation layer; and a spacer on a side of the passivation layer distal from the first base substrate and in contact with the passivation layer. A method for preparing the liquid crystal writing screen is further provided.

Abstract: A display baseplate includes a display region and a peripheral region, and the display baseplate includes: a substrate, and a gate line driving circuit, a plurality of signal lines, and a gate line provided on one side of the substrate, the gate line driving circuit and the plurality of signal lines all being located in the peripheral region, and the gate line being located in the display region. The gate line driving circuit is respectively connected to the plurality of signal lines and the gate line, and includes a plurality of stages of driving units that are cascaded to each other, each driving unit includes a first element group, and the first element group includes at least one first electronic element. The plurality of signal lines are arranged in a first direction, the first direction is an extending direction of the gate line.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: The embodiment of the present disclosure provides a display substrate including a plurality of gate lines and a plurality of data lines. The plurality of gate lines each extend along a first direction, and the plurality of data lines each extend along a second direction. The plurality of data lines are spatially crossed with the plurality of gate lines to define a plurality of pixel regions, and at least one sub-pixel is provided in each of the plurality of pixel regions. At least three sub-pixels adjacent to each other along the second direction form one of a plurality of pixels. All the sub-pixels within one of the plurality of pixels are coupled to a same data line of the plurality of data lines.

Abstract: An array substrate includes a base substrate, including a display area and a peripheral area; a driving circuit layer, located at one side of the base substrate and including a plurality of data lines and a plurality of scanning lines, where the plurality of data lines extend along a first direction and are arranged at intervals along a second direction, the plurality of scanning lines extend along the second direction and are arranged at intervals along the first direction, and the data line and the scanning line intersect with each other to define a plurality of sub-pixel areas; and a metal layer, located at one side of the driving circuit layer away from the base substrate, where the metal layer includes a plurality of metal blocks arranged at intervals, and the metal block is located at an intersection of the data line and the scanning line.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: Disclosed are a display substrate, a display panel and a display device. The display substrate includes: a base substrate, multiple gate-line groups, multiple data lines, the multiple data line include: first type of data lines and second type of data lines alternately arranged along the first direction; multiple transistors, transistors in the same sub-transistor group are connected with the same gate line, transistors in adjacent sub-transistor groups are connected with different gate lines, and transistors of the same sub-transistor group are connected with different data lines; multiple pins, the multiple pins include: first type of pins and second type of pins alternately arranged along the first direction; two adjacent first type of data lines are connected with a same first type of pin, and adjacent second type of data lines are connected with a same second type of pin.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A shift-register unit, a grid driving circuit and a displaying device, which relates to the technical field of displaying. In the present disclosure, the oxide-semiconductor layers of the oxide thin-film transistors may be delimited into regions according to the total channel widths and the channel lengths required by the oxide thin-film transistors in the shift-register unit, wherein the sum of the widths of the independent semiconductor branches obtained by the delimitation is equal to the required total channel width. Accordingly, one oxide thin-film transistor can realize the required total channel width by using the one or more semiconductor branches, to ensure the normal operation of the oxide thin-film transistor, whereby the oxide-semiconductor layers of the different oxide thin-film transistors can be configured differently, to realize the purpose of reducing the border frame of the displaying device.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: The present disclosure provides a GOA circuit, an array substrate and a display device, wherein the GOA circuit comprises: a GOA area, and the GOA area comprises a plurality of GOA unit circuits cascaded with each other; a lead area, wherein at least one STV signal line and at least one non-STV signal line are arranged in the lead area, each STV signal line and each non-STV signal line is connected to at least one GOA unit circuit, and the non-STV signal line comprises at least one of a Vdd signal line, a Clk signal line, a VGH signal line and a VGL signal line; a projection of the at least one STV signal line on the lead area does not overlap a projection of the at least one non-STV signal line on the lead area.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a common electrode. The common electrode includes an electrode unit array. The electrode unit array includes a plurality of electrode units. Each of the electrode units corresponds to two adjacent sub-pixels. Each of the electrode units includes a boundary electrode line and an inner region defined by the boundary electrode line. The inner region includes a first region and a second region. The first region includes a plurality of first strip electrode lines having a same longitudinal direction. Two adjacent first strip electrode lines are not connected inside the first region. The second region includes a plurality of second strip electrode lines having a same longitudinal direction. Two adjacent second strip electrode lines are not connected inside the second region.

Abstract: The present disclosure provides a display substrate and a display device. The display substrate includes a common electrode. The common electrode includes an electrode unit array. The electrode unit array includes a plurality of electrode units. Each of the electrode units corresponds to two adjacent sub-pixels. Each of the electrode units includes a boundary electrode line and an inner region defined by the boundary electrode line. The inner region includes a first region and a second region. The first region includes a plurality of first strip electrode lines having a same longitudinal direction. Two adjacent first strip electrode lines are not connected inside the first region. The second region includes a plurality of second strip electrode lines having a same longitudinal direction. Two adjacent second strip electrode lines are not connected inside the second region.

Abstract: A display substrate and a display device are disclosed. The display substrate includes a base substrate and a plurality of shift register units; each of the plurality of shift register units includes an input circuit, an output circuit, a first reset circuit and a frame reset signal connection wire; the frame reset signal connection wire and is configured to provide a frame reset signal to the first reset circuit; the first reset circuit is configured to respond to the frame reset signal, so as to reset a first node and an output end within a time period between two display frames of the display substrate; the first reset circuit includes a first transistor and a second transistor, and the frame reset signal connection wire, a gate of the first transistor and a gate of the second transistor are provided on a first conductive layer.

Abstract: A shift register includes an input sub-circuit, a first noise reduction sub-circuit, and a first pull-down sub-circuit. The first noise reduction sub-circuit is coupled to the pull-up node, the first pull-down node and a first voltage signal terminal, and is configured to transmit a first voltage signal to the pull-up node under control of the first pull-down node; the input sub-circuit is coupled to the pull-up node and a signal input terminal, and is configured to transmit an input signal to the pull-up node in response to the input signal; the first pull-down sub-circuit is coupled to the signal input terminal, the first pull-down node and the first voltage signal terminal, and is configured to transmit the first voltage signal to the first pull-down node in response to the input signal, so that the first noise reduction sub-circuit stops transmitting the first voltage signal to the pull-up node.

Abstract: Disclosed are a gate driving circuit and a display device. According to the gate driving circuit, in every five adjacent shift registers, the output control end of the first shift register is electrically connected to the input signal end of the fifth shift register; in every six adjacent shift registers, the output control end of the sixth shift register is electrically connected to the reset signal end of the first shift register.