Abstract: A shift register, a method for driving the same, a gate driving circuit, and a display device are described. The shift register includes a pull-up control circuit which outputs the voltage of a signal input terminal, a pull-up circuit which outputs the voltage of a first clock signal input terminal, a pull-down control circuit which outputs the voltage of a second clock signal input terminal, or pulls down the voltage of the pull-down node, a pull-down circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, a reset circuit which pulls down voltages of the pull-up node and the signal output terminal to the first voltage terminal, respectively, and a noise reduction control circuit which outputs the voltage of a noise reduction control signal terminal to the pull-down node in the blanking time of an image frame.

Abstract: The present disclosure provides an anti-reflective substrate and a method for preparing the same, an array substrate, and a display device. The anti-reflective substrate includes a base substrate and an anti-reflective film having an optical path control structure. The anti-reflective film is disposed on the base substrate, and the optical path control structure is configured to reduce a reflection of an incident light from a side of the base substrate on which the anti-reflective film is disposed.

Abstract: The present disclosure provides a drift control circuit, a drift control method, a gate driving unit, a gate driving method and a display device. The drift control circuit includes: a first drift control sub-circuit configured to, during noise releasing performed by the first pull-down module, control first electrodes of pull-down transistors included in the second pull-down module to be coupled to a first control voltage terminal, which is configured to input a first voltage to the first pull-down module during noise releasing performed by the first pull-down module; and a second drift control sub-circuit configured to, during noise releasing performed by the second pull-down module, control first electrodes of pull-down transistors included in the first pull-down module to be coupled to a second control voltage terminal, which is configured to input the first voltage to the second pull-down module during noise releasing performed by the second pull-down module.

Abstract: A shift register unit, a shift register circuit and a display panel is provided. The shift register unit includes: an input circuit configured to transmit a power signal to the pull-up node; an output circuit configured to transmit a clock signal to the signal output terminal; a reset circuit configured to transmit a reference signal to the pull-up node and the signal output terminal; a first pull-down control circuit configured to transmit the reference signal to the pull-down control node and the pull-down node; a second pull-down control circuit configured to transmit the power signal to the pull-down control node and the pull-down node; and a pull-down circuit configured to transmit the reference signal to the pull-up node and the signal output terminal.

Abstract: The present application discloses a gate driving circuit having multiple shift register units cascaded one after another in multiple stages. The multiple shift register units are grouped into a plurality of groups of shift register units, each of the plurality of groups of shift register units having a plurality of shift register units. Each of the plurality of groups of shift register units includes a single pull-down control sub-circuit.

Abstract: There is provided a surface treatment method of a glass substrate having a pit on a surface thereof, a production method of an array substrate comprising this method, and an array substrate. The method includes: forming a layer of SiO2 sol at least at a side wall of the pit; and drying the layer of SiO2 sol to form a smoothening layer so as to smoothen an upper edge and a lower edge of the side wall of the pit.

Abstract: There is provided in the present disclosure a shift register unit, including: an input sub-circuit, whose first terminal is coupled to an input signal terminal, and second terminal is coupled to a pull-up node; an output sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to a clock signal terminal, and third terminal is coupled to an output terminal, and configured to output a clock signal of the clock signal terminal to the output terminal under the control of a level signal of the pull-up node; a first electro-static discharge sub-circuit, whose first terminal is coupled to the pull-up node, second terminal is coupled to an electro-static discharge control terminal, and third terminal is coupled to a ground, and configured to discharge static electricity accumulated at the pull-up node under the control of a level signal of the electro-static discharge control terminal.

Abstract: A shift register circuit includes a first output sub-circuit, and a second output sub-circuit. The first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of the control signal output via a control signal terminal and the potential of the pull-up node. The second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.

Abstract: Embodiments of the disclosure provide a gate driver, a display apparatus and a method for controlling the gate driver. The gate driver comprises a plurality of clock signal terminals; a controlling signal terminal; and N stages of cascaded gate driving circuits. Each of the N stages of cascaded gate driving circuits is configured to pull-up a voltage of an outputting terminal of the gate driving circuit according to a signal at the respective clock signal terminal, and to perform a noise reduction operation according to a signal at the controlling signal terminal. A controller is coupled with the clock signal terminals and the controlling signal terminal, and is configured to detect signals at the plurality of clock signal terminals, and to output a valid level signal to the controlling signal terminal in response to the signal at the clock signal terminal being abnormal.

Abstract: Embodiments of the present disclosure invention disclose an inversion control circuit, a method for driving the same, a display panel, and a display device, and the inversion control circuit includes: an input circuit, a switching control circuit, a first output circuit, and a second output circuit. In the inversion control circuit according to the embodiment of the present disclosure, the four circuits cooperate with each other to thereby enable the potential of an input signal end to be opposite to the potential of an inverted signal output end, so that when the inversion control circuit is applicable to the display panel, a clock signal is used as an input signal, and an output signal is a clock signal opposite in phase.

Abstract: A shift register unit and a method for driving the same, a gate driving circuit, and a display apparatus are disclosed. The shift register unit includes: an input circuit configured to transmit an input signal to a pull-up node; an output circuit configured to transmit a clock signal to an output signal terminal under control of a voltage at the pull-up node; a first reset circuit configured to reset the pull-up node to a first level under control of a first reset signal; a first pull-down control circuit configured to control levels at the pull-up node and the output signal terminal under control of a first control signal; and a first voltage control circuit electrically connected to a second control signal terminal, and configured to control a voltage signal waveform at the first pull-down node under control of a second control signal.

Abstract: A shift register circuit includes a first output sub-circuit, and a second output sub-circuit. The first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of the control signal output via a control signal terminal and the potential of the pull-up node. The second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.

Abstract: The present disclosure is related to an array substrate. The array substrate may include a plurality of gate lines, a plurality of data lines intersecting the gate lines, and a first gate driving circuit comprising a plurality of shift register circuits in a non-active area. The gate lines and the data lines may define a plurality of sub-pixels in an active area and a plurality of dummy sub-pixels in the non-active area adjacent to the active area. The first gate driving circuit may be farther away from the active area than the plurality of the dummy sub-pixels. At least one of the dummy sub-pixels may include an auxiliary capacitor. A shift register circuit in the first gate driving circuit may be coupled to the auxiliary capacitor. The auxiliary capacitor may form at least a part of a bootstrap capacitor in the shift register circuit.

Abstract: A pixel structure and a driving method thereof, a display panel and a display device are provided. The pixel structure includes a pixel electrode, a gate line, a data line, a first thin film transistor and a second thin film transistor. A gate electrode of the first thin film transistor is electrically connected with the gate line, a first electrode of the first thin film transistor is electrically connected with the data line, a gate electrode of the second thin film transistor is electrically connected with a first electrode of the second thin film transistor, the first electrode of the second thin film transistor is electrically connected with the pixel electrode, and a second electrode of the second thin film transistor is electrically connected with a second electrode of the first thin film transistor.

Abstract: Embodiments of the present disclosure invention disclose an inversion control circuit, a method for driving the same, a display panel, and a display device, and the inversion control circuit includes: an input circuit, a switching control circuit, a first output circuit, and a second output circuit. In the inversion control circuit according to the embodiment of the present disclosure, the four circuits cooperate with each other to thereby enable the potential of an input signal end to be opposite to the potential of an inverted signal output end, so that when the inversion control circuit is applicable to the display panel, a clock signal is used as an input signal, and an output signal is a clock signal opposite in phase.

Abstract: The present disclosure provides an anti-reflective substrate and a method for preparing the same, an array substrate, and a display device. The anti-reflective substrate includes a base substrate and an anti-reflective film having an optical path control structure. The anti-reflective film is disposed on the base substrate, and the optical path control structure is configured to reduce a reflection of an incident light from a side of the base substrate on which the anti-reflective film is disposed.

Abstract: There is provided a surface treatment method of a glass substrate having a pit on a surface thereof, a production method of an array substrate comprising this method, and an array substrate. The method includes: forming a layer of SiO2 sol at least at a side wall of the pit; and drying the layer of SiO2 sol to form a smoothening layer so as to smoothen an upper edge and a lower edge of the side wall of the pit.

Abstract: Embodiments of the disclosure provide a gate driver, a display apparatus and a method for controlling the gate driver. The gate driver comprises a plurality of clock signal terminals; a controlling signal terminal; and N stages of cascaded gate driving circuits. Each of the N stages of cascaded gate driving circuits is configured to pull-up a voltage of an outputting terminal of the gate driving circuit according to a signal at the respective clock signal terminal, and to perform a noise reduction operation according to a signal at the controlling signal terminal. A controller is coupled with the clock signal terminals and the controlling signal terminal, and is configured to detect signals at the plurality of clock signal terminals, and to output a valid level signal to the controlling signal terminal in response to the signal at the clock signal terminal being abnormal.

Abstract: Embodiments of the present disclosure provide a shift register, a gate driving circuit, a display panel and a display apparatus. The shift register comprises an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, and a first discharging controlling sub-circuit. The first discharging controlling sub-circuit is coupled to a first controlling signal inputting terminal, a second controlling signal inputting terminal and a signal outputting terminal, and configured to provide a second controlling signal from the second controlling signal inputting terminal to the signal outputting terminal under a control of a first controlling signal from the first controlling signal inputting terminal. The signal outputting terminal is set to a high level by inputting the first controlling signal and the second controlling signal to the shift register.

Abstract: A touch display panel includes a plurality of gate lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction; and a plurality of pixels at intersections of the gate lines and the data lines. Each of the pixels includes a pixel electrode and a common electrode opposite to the pixel electrode. The common electrodes are distributed in a plurality of touch regions arranged in an array and independent of each other. Each of the touch regions includes at least one connecting line extending in the first direction and a respective touch signal line electrically connected to the at least one connecting line and extending in the second direction. Each of the at least one connecting line electrically connects together respective ones of the plurality of common electrodes.