Patents by Inventor Xiaoyuan Wang

Xiaoyuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10101649
    Abstract: A mask plate is disclosed. The mask plate includes a via hole pattern, the via hole pattern includes a body portion and at least two protruding portions extending outward from the body portion; a dimension of the body portion is greater than a resolution dimension of an exposure machine, and each of the protruding portions includes a first protruding portion having a dimension greater than the resolution dimension of the exposure machine. Upon exposure of the mask plate, the protruding portions themselves and zones between adjacent protruding portions form convex portions and concave portions of a via hole, respectively; in this way, a circumstance and also an edge area of the via hole as formed is increased and an electric resistance of the via hole is reduced effectively.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: October 16, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQUING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yajie Bai, Xiaoyuan Wang, Jaikwang Kim, Fei Shang
  • Publication number: 20180212001
    Abstract: The present disclosure provides a pixel structure and a fabricating method thereof, as well as a display panel and a display apparatus. The pixel structure includes a plurality of pairs of pixels in a matrix having rows and columns; each pixel is shaped as a right triangle and corresponds to one of four different colors; each pair of pixels is at an intersection between a row and a column and comprises two pixels of different colors; and two pairs of pixels at two neighboring intersections along a direction of the rows or along a direction of the columns comprise four pixels of different colors. Each pair of pixels can have a combined shape of a rectangle, which can form a virtual pixel unit. Adjacent four pixels of four different colors have a combined shape of diamond, which can form a physical pixel unit.
    Type: Application
    Filed: May 20, 2016
    Publication date: July 26, 2018
    Applicants: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yajie BAI, Zhuo XU, Xiaoyuan WANG, Jaikwang KIM
  • Publication number: 20180190216
    Abstract: The array substrate comprises a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units arranged as an array. Each of the plurality of data lines is arranged between two columns of pixel units, the two columns of the pixel units extending in the second direction and being adjacent to each other in the first direction, and the data line is connected to pixel units at one side of said data line or to pixel units at the other side of said data line. Each of the plurality of data lines switches the direction of connection from one side to the other in an alternating manner with each two adjacent rows of pixel units, and the plurality of data lines have the same connection direction in each row of pixel units.
    Type: Application
    Filed: January 26, 2016
    Publication date: July 5, 2018
    Inventors: Xiaoyuan Wang, Wu Wang, Jaikwang Kim, Zhuo Xu, Yajie Bai
  • Patent number: 9888590
    Abstract: A printed circuit board, a display panel and a wiring method are provided by embodiments of the disclosure. The printed circuit board includes: a first multichannel circuit connecting terminal; a second multichannel circuit connecting terminal; and a plurality of connecting wires connecting a plurality of second channel connecting pins of the second multichannel circuit connecting terminal with a part of a first channel connecting pins of the first multichannel circuit connecting terminal in one-to-one correspondence, the rest of the first channel connecting pins being spare, where at least one of the plurality of connecting wires has a first portion, which is bent to extend through a spare region, on the printed circuit board, between the spare first channel connecting pins and the second multichannel circuit connecting terminal.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: February 6, 2018
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhuo Xu, Yajie Bai, Xiaoyuan Wang, Jaikwang Kim
  • Publication number: 20170257957
    Abstract: A printed circuit board, a display panel and a wiring method are provided by embodiments of the disclosure. The printed circuit board includes: a first multichannel circuit connecting terminal; a second multichannel circuit connecting terminal; and a plurality of connecting wires connecting a plurality of second channel connecting pins of the second multichannel circuit connecting terminal with a part of a first channel connecting pins of the first multichannel circuit connecting terminal in one-to-one correspondence, the rest of the first channel connecting pins being spare, where at least one of the plurality of connecting wires has a first portion, which is bent to extend through a spare region, on the printed circuit board, between the spare first channel connecting pins and the second multichannel circuit connecting terminal.
    Type: Application
    Filed: August 19, 2016
    Publication date: September 7, 2017
    Inventors: Zhuo Xu, Yajie Bai, Xiaoyuan Wang, Jaikwang Kim
  • Publication number: 20170200739
    Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate has a display region and a wiring region located on a periphery of the display region. The array substrate includes a base substrate, and a transparent conductive strip and a wire formed on the base substrate in the wiring region; the transparent conductive strip and the wire are located in different layers and are in direct contact with each other, and the wire has one or more exposure holes formed therein.
    Type: Application
    Filed: September 7, 2016
    Publication date: July 13, 2017
    Inventors: Xiaoyuan WANG, Wu WANG, Rui WANG, Yajie BAI, Zhuo XU
  • Publication number: 20170149753
    Abstract: The present disclosure provides a hotspot information analysis method and apparatus and a computer storage medium. The hotspot information analysis method comprises: extracting, from Internet data, hotspot data describing a hotspot event; performing analysis for association of business data in the whole business market related to a business transaction and the hotspot data, and obtaining a correspondence relationship between candidate hotspot data and candidate business data, wherein the candidate hotspot data refers to hotspot data in the hotspot data related to the business transaction, and the candidate business data refers to business data in the business data related to the hotspot event; merging and processing the candidate hotspot data according to the correspondence relationship between the candidate hotspot data and candidate business data, and obtaining target hotspot data and target business data corresponding to the target hotspot data.
    Type: Application
    Filed: January 14, 2015
    Publication date: May 25, 2017
    Applicant: BAIDU ONLINE NETWORK TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Xiaoyuan Wang, Chengze CHEN, Haoping QIU, Yang WANG, Jinhua TANG
  • Publication number: 20170123307
    Abstract: A mask plate is disclosed. The mask plate includes a via hole pattern, the via hole pattern includes a body portion and at least two protruding portions extending outward from the body portion; a dimension of the body portion is greater than a resolution dimension of an exposure machine, and each of the protruding portions includes a first protruding portion having a dimension greater than the resolution dimension of the exposure machine. Upon exposure of the mask plate, the protruding portions themselves and zones between adjacent protruding portions form convex portions and concave portions of a via hole, respectively; in this way, a circumstance and also an edge area of the via hole as formed is increased and an electric resistance of the via hole is reduced effectively.
    Type: Application
    Filed: October 20, 2016
    Publication date: May 4, 2017
    Inventors: Zhuo XU, Yajie BAI, Xiaoyuan WANG, Jaikwang KIM, Fei SHANG
  • Publication number: 20170092211
    Abstract: There is provided an array substrate and display driving method thereof, and a display device, wherein the array substrate comprises a common voltage line, a plurality of pixel electrodes arranged in rows and columns, and at least one first transistor arranged between two adjacent pixel electrodes, wherein a gate electrode of first transistor is coupled to the common voltage line, a first electrode of the first transistor is coupled to one of the two adjacent pixel electrodes, and a second electrode of the first transistor is coupled to the other one of the two adjacent pixel electrodes. The disclosure makes it possible to achieve polarity neutralization of grayscale voltages for the adjacent pixels without reducing the pixel aperture ratio, thus significantly reducing power consumption without affecting the display effect and achieving a power consumption even lower than the lowest power consumption achieved by the existing display devices.
    Type: Application
    Filed: April 29, 2016
    Publication date: March 30, 2017
    Inventors: Zhuo XU, Xiaoyuan WANG, Yajie BAI, Rui WANG, Wu WANG, Jaikwang KIM
  • Publication number: 20150263020
    Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate and an electrostatic discharge (ESD) protection device disposed on the semiconductor substrate. The ESD protection device includes a source and a drain disposed in the semiconductor substrate, a gate disposed on the semiconductor substrate between the source and the drain, and a p-type doped region disposed in the drain.
    Type: Application
    Filed: February 2, 2015
    Publication date: September 17, 2015
    Inventors: Xiaoyuan WANG, Chuanmiao ZHOU, Fengji JIN, Hongwei LI, Bing GUO, Zhiguang GUO
  • Patent number: 5698723
    Abstract: Disclosed is a process for the preparation of bistriphenylsilyl chromate, wherein triphenylchlorosilane, potassium dichromate and any one selected from alkali metal oxides, alkali hydroxides and alkali metal carbonates are reacted in, as solvent, a mixture of glacial acetic acid and a hydrocarbon solvent at a certain temperature, whereby bistriphenylsilyl chromate having high purity can be obtained with high yield.
    Type: Grant
    Filed: August 16, 1996
    Date of Patent: December 16, 1997
    Assignees: China Paeto-Chemical Corporation, Research Institute of Petroleum Processing SINOPEC
    Inventors: Longxiu Dai, Qiwei Duan, Hongbo Ji, Xiaoyuan Wang, Jinqiang Mo, Jinfeng Wang, Hongmei Liu, Xiuqin Li, Jiuhua Chen, Ping Gao