Patents by Inventor Xijiang Lin
Xijiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11635462Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.Type: GrantFiled: August 27, 2020Date of Patent: April 25, 2023Assignee: Siemens Industry Software Inc.Inventors: Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
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Publication number: 20220065929Abstract: This application discloses a computing system implementing an automatic test pattern generation tool to convert a transistor-level model of a library cell describing a digital circuit into a switch-level model of the library cell, generate test patterns configured to enable detection of target defects injected into the switch-level model of the library cell, and bifurcate the test patterns into a first subset of the test patterns and a second set of the test patterns based on detection types for the target defects enabled by the test patterns. The computing system can implement a cell model generation tool to perform an analog simulation of the transistor-level model of the library cell using the second subset of the test patterns to verify that they enable detection of target defects, while skipping performance of the analog simulation of the transistor-level model of the library cell using the first subset of the test patterns.Type: ApplicationFiled: August 27, 2020Publication date: March 3, 2022Inventors: Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
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Patent number: 10977400Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.Type: GrantFiled: August 22, 2019Date of Patent: April 13, 2021Assignee: Mentor Graphics CorporationInventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
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Publication number: 20200410065Abstract: Systems and methods for a deterministic automatic test generation (ATPG) process including Timing Exception ATPG (TEA). A method includes performing an automated test pattern generation (ATPG) process that uses timing exception information to generate a test pattern for a targeted fault of a circuit design with at least one timing exception path. The method includes testing the targeted fault of the circuit design using the test pattern to produce a test result for the targeted fault.Type: ApplicationFiled: August 22, 2019Publication date: December 31, 2020Inventors: Wu-Tung Cheng, Kun-Han Tsai, Naixing Wang, Chen Wang, Xijiang Lin, Mark A. Kassab, Irith Pomeranz
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Patent number: 10509073Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 31, 2017Date of Patent: December 17, 2019Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 10372855Abstract: Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.Type: GrantFiled: February 27, 2015Date of Patent: August 6, 2019Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Ting-Pu Tai, Wu-Tung Cheng, Takeo Kobayashi
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Patent number: 10222420Abstract: Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.Type: GrantFiled: January 6, 2017Date of Patent: March 5, 2019Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
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Publication number: 20180045780Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 31, 2017Publication date: February 15, 2018Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 9720040Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: July 20, 2015Date of Patent: August 1, 2017Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20170193155Abstract: Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.Type: ApplicationFiled: January 6, 2017Publication date: July 6, 2017Inventors: Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
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Patent number: 9568552Abstract: The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.Type: GrantFiled: June 6, 2014Date of Patent: February 14, 2017Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Janusz Rajski
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Patent number: 9501589Abstract: Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified.Type: GrantFiled: October 17, 2014Date of Patent: November 22, 2016Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Yu Huang, Wu-Tung Cheng
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Patent number: 9335374Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.Type: GrantFiled: December 2, 2014Date of Patent: May 10, 2016Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
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Publication number: 20150323600Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Applicant: MENTOR GRAPHICS CORPORATIONInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20150248515Abstract: Various aspects of the disclosed technology relate to techniques of selecting scan cells from state elements for partial scan designs. Signal probability values for logic gates in a circuit design are first determined. Based on the signal probability values, next-state capture probability values for state elements in the circuit design are computed. Based on the next-state capture probability values, scan cells are selected from the state elements. Scan cells may be further selected based on continuously-updated control weight values and observation weight values associated with the state elements.Type: ApplicationFiled: February 27, 2015Publication date: September 3, 2015Inventors: Xijiang Lin, Ting-Pu Tai, Wu-Tung Cheng, Takeo Kobayashi
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Patent number: 9086454Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 14, 2013Date of Patent: July 21, 2015Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20150153410Abstract: Various aspects of the disclosed techniques relate to using dynamic shift for test pattern compression. Scan chains are divided into segments. Non-shift clock cycles are added to one or more segments to make an uncompressible test pattern compressible. The one or more segments may be selected based on compressibility, the number of specified bits and/or the location on the scan chains. A dynamic shift controller may be employed to control the dynamic shift.Type: ApplicationFiled: December 2, 2014Publication date: June 4, 2015Inventors: Xijiang Lin, Mark A. Kassab, Janusz Rajski
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Patent number: 8996941Abstract: Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.Type: GrantFiled: June 10, 2013Date of Patent: March 31, 2015Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Janusz Rajski
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Publication number: 20150040087Abstract: Aspects of the disclosed techniques relate to techniques for identifying power sensitive scan cells. Signal probability values for signal lines in a circuit design are first computed, wherein the signal lines comprise signal lines associated with scan cells in the circuit design. Toggling probability values are then computed based on the signal probability values, wherein the toggling probability values comprise toggling rate values for the scan cells. Toggling rate reduction values are then computed based on the toggling probability values, wherein the toggling rate reduction values comprise toggling rate reduction values for the scan cells. Finally, scan cells having high toggling rate reduction values are identified.Type: ApplicationFiled: October 17, 2014Publication date: February 5, 2015Inventors: Xijiang Lin, Yu Huang, Wu-Tung Cheng
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Publication number: 20140365840Abstract: The test circuitry according to various aspects of the presently disclosed techniques comprises: low-toggling pseudo-random test pattern generation circuitry, wherein the low-toggling pseudo-random test patterns generated by the low-toggling pseudo-random test pattern generation circuitry causing switching activity during scan shift cycles lower than pseudo-random test patterns generated by a pseudo-random pattern generator; scan chains configurable to shift in a low-toggling pseudo-random test pattern generated by the low-toggling pseudo-random test pattern generation circuitry; background chains configurable to shift in a background test pattern; and weight insertion circuitry configurable to modify a plurality of bits in the low-toggling pseudo-random test pattern based on bits in the background test pattern to form a weighted pseudo-random test pattern.Type: ApplicationFiled: June 6, 2014Publication date: December 11, 2014Inventors: Xijiang Lin, Janusz Rajski