Patents by Inventor Xijiang Lin
Xijiang Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8890563Abstract: Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.Type: GrantFiled: May 7, 2009Date of Patent: November 18, 2014Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Janusz Rajski
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Publication number: 20140047404Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: October 14, 2013Publication date: February 13, 2014Applicant: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20130332786Abstract: Background scan cells are selected from scan cells in a circuit based on specified bit distribution information for a plurality of test cubes generated for testing the circuit. A main portion and a background portion are then determined for each test cube in the plurality of test cubes. The background portion corresponds to the background scan cells. Test cubes in the plurality of test cubes that have compatible main portions are merged into test cube groups. Each test cube group in the test cube groups comprises a main test cube and background test cubes. A main test cube, supplied by a tester or a decompressor, may be shifted into the scan chains. A background test cube may be shifted into background chains and be inserted into the main test cube in the scan chains based on control signals.Type: ApplicationFiled: June 10, 2013Publication date: December 12, 2013Inventors: Xijiang Lin, Janusz Rajski
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Patent number: 8560906Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: October 31, 2011Date of Patent: October 15, 2013Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Patent number: 8499209Abstract: Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.Type: GrantFiled: April 22, 2010Date of Patent: July 30, 2013Assignee: Mentor Graphics CorporationInventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Mark A Kassab, Xijiang Lin
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Patent number: 8290738Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: GrantFiled: March 16, 2011Date of Patent: October 16, 2012Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
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Publication number: 20120174049Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: October 31, 2011Publication date: July 5, 2012Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20120043991Abstract: Selective blocking is applied to discrete segments of scan chains in the integrated circuit device. In some implementations, locking components associated with the scan segments are selectively activated according to blocking data incorporated in test pattern data. In other implementations, selective blocking is applied to the scan cells identified as causing the highest power consumption. Selective incorporation of blocking components in an integrated circuit device is based on statistical estimation of scan cell transition rates. When the blocking components are enabled, pre-selected signal values are presented to the functional logic of the integrated circuit device. At the same time, propagation of output value transitions that may take place in the scan cells is prevented.Type: ApplicationFiled: May 7, 2009Publication date: February 23, 2012Inventors: Xijiang Lin, Janusz Rajski
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Patent number: 8051352Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: GrantFiled: April 27, 2007Date of Patent: November 1, 2011Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20110166818Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Inventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
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Patent number: 7925465Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: GrantFiled: February 12, 2008Date of Patent: April 12, 2011Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
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Patent number: 7865792Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.Type: GrantFiled: February 9, 2010Date of Patent: January 4, 2011Assignee: Mentor Graphics CorporationInventors: Xijiang Lin, Janusz Rajski
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Publication number: 20100275077Abstract: Test patterns for at-speed scan tests are generated by filling unspecified bits of test cubes with functional background data. Functional background data are scan cell values observed when switching activity of the circuit under test is near a steady state. Hardware implementations in EDT (embedded deterministic test) environment are also disclosed.Type: ApplicationFiled: April 22, 2010Publication date: October 28, 2010Inventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Mark A. Kassab, Xijiang Lin
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Publication number: 20100146350Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.Type: ApplicationFiled: February 9, 2010Publication date: June 10, 2010Inventors: Xijiang Lin, Janusz Rajski
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Patent number: 7685491Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.Type: GrantFiled: April 5, 2007Date of Patent: March 23, 2010Inventors: Xijiang Lin, Janusz Rajski
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Publication number: 20080195346Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.Type: ApplicationFiled: February 12, 2008Publication date: August 14, 2008Inventors: Xijiang Lin, Dariusz Czysz, Mark Kassab, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
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Publication number: 20070288822Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.Type: ApplicationFiled: April 27, 2007Publication date: December 13, 2007Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
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Publication number: 20070250749Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems used for generating test patterns as may be used as part of a test pattern generation process (for example, for use with an automatic test pattern generator (ATPG) software tool). In one exemplary embodiment, hold probabilities are determined for state elements (for example, scan cells) of a circuit design. A test cube is generated targeting one or more faults in the circuit design. In one particular implementation, the test cube initially comprises specified values that target the one or more faults and further comprises unspecified values. The test cube is modified by specifying at least a portion of the unspecified values with values determined at least in part from the hold probabilities and stored.Type: ApplicationFiled: April 5, 2007Publication date: October 25, 2007Inventors: Xijiang Lin, Janusz Rajski
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Patent number: 6378096Abstract: A method of solving a test generation problem for sequential circuits is disclosed. The method comprises recursively dividing an original test generation problem into smaller problems, wherein said sub-problems may be dependent while one or more of said dependent sub-problems may have solution-specific independence, finding solutions for said sub-problems, reusing solutions for dependent sub-problems, whenever the dependent sub-problems enjoy solution-specific independence; and identifying a minimal subset of conflicting objectives if a sub-problem that has to be solved to achieve multiple objectives has no solution. A test generation system comprising a computer, said computer having a cpu and memory, said memory comprising instructions capable of implementing components of said system.Type: GrantFiled: September 3, 1999Date of Patent: April 23, 2002Assignee: NEC USA, Inc.Inventors: Srimat T. Chakradhar, Kiran B. Doreswamy, Surendra K. Bommu, Xijiang Lin