Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Abstract: Disclosed is a post-plating treatment method for a one-step brass-electroplated steel wire, comprising the following steps: electroplating the surface of the steel wire with a brass alloy; immediately washing the electroplated steel wire with cold water, removing residues from the surface of the steel wire, and blow-drying the steel wire with cold air; immersing the blow-dried steel wire in a water-based coating solution; and taking the immersed steel wire out, blow-drying the steel wire with natural air, and taking the steel wire up. The water-based coating solution comprises a polyoxyethylene organic salt, sodium hypophosphite and the balance of pure water, the polyoxyethylene organic salt comprising a salt of alkyl polyoxyethylene ether phosphate and polyoxyethylene alkylamine.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: Systems for obtaining an image of a target are provided including at least one multi-wavelength illumination module configured to illuminate a target using two or more different wavelengths, each penetrating the target at different depths; a multi-wavelength camera configured to detect the two or more different wavelengths illuminating the target on corresponding different channels and acquire corresponding images of the target based on the detected two or more different wavelengths illuminating the target; a control module configured synchronize illumination of the target by the at least one multi-wavelength illumination module and detection of the two or more different wavelengths by the camera; an analysis module configured to receive the acquired images of the target and analyze the acquired images to provide analysis results; and an image visualization module modify the acquired images based on the analysis results to provide a final improved image in real-time.

Abstract: In some embodiments, the present disclosure relates to a method that includes aligned a first wafer with a second wafer. The second wafer is spaced apart from the first wafer. The first wafer is arranged on a first electrostatic chuck (ESC). The first ESC has electrostatic contacts that are configured to attract the first wafer to the first ESC. Further, the second wafer is brought toward the first wafer to directly contact the first wafer at an inter-wafer interface. The inter-wafer interface is localized to a center of the first wafer. The second wafer is deformed to gradually expand the inter-wafer interface from the center of the first wafer toward an edge of the first wafer. The electrostatic contacts of the first ESC are turned OFF such that the first and second wafers are bonded to one another by the inter-wafer interface.

Abstract: Disclosed is a keyboard for an information handling system. The keyboard includes a top cover comprising a polyester and a plurality of jute fibers, a keycap assembly comprising one or more keycaps, and a bottom cover comprising a first polylactic acid (PLA) and a post-consumer resin (PCR). The keycap assembly can be positioned between the top cover and the bottom cover, and the top cover can include one or more openings keycap assembly keycaps to protrude through.

Abstract: Provided are a chimeric antigen receptor capable of targeting B7-H3, a nucleic acid molecule encoding the chimeric antigen receptor, a nucleic acid construct comprising the nucleic acid molecule, an immune effector cell expressing the chimeric antigen receptor, and use thereof. The chimeric antigen receptor comprises an anti-B7-H3 binding domain, a hinge region, a transmembrane domain and a signal transduction domain. Further provided are a composition and a method for diagnosing, treating or preventing tumors that express B7-H3.

Abstract: A composite carbon fiber laminate, including a first carbon fiber woven fabric layer, including one or more first voids defined between fabric strands of the first carbon fiber woven fabric layer; a second carbon fiber woven fabric layer, including one or more second voids defined between fabric strands of the second carbon fiber woven fabric layer; a core fabric layer; a first reflective layer positioned between the first carbon fiber woven fabric layer and the core fabric layer; and a second reflective fabric layer positioned between the second carbon fiber woven fabric layer and the core fabric layer, wherein the first reflective layer reflects light that is incident upon the first carbon fiber woven fabric layer at the one or more first voids.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes bonding structure arranged directly between a first substrate and a second substrate. The first substrate includes a first transparent material and a first alignment mark. The first alignment mark is arranged on an outer region of the first substrate and also includes the first transparent material. The first alignment mark is defined by surfaces of the first substrate that are arranged between an uppermost surface of the first substrate and a lowermost surface of the first substrate. The second substrate includes a second alignment mark on an outer region of the second substrate. The second alignment mark directly underlies the first alignment mark, and the bonding structure is arranged directly between the first alignment mark and the second alignment mark.

Abstract: An embodiment low contamination chamber includes a gas inlet, an adjustable top electrode, and an adjustable bottom electrode. The low contamination chamber is configured to adjust a distance between the adjustable top electrode and the adjustable bottom electrode in response to a desired density of plasma and a measured density of plasma measured between the adjustable top electrode and the adjustable bottom electrode during a surface activation process. The low contamination chamber further includes an outlet.

Abstract: A microelectromechanical system device includes a substrate, a dielectric layer, an electrode, a surface modification layer and a membrane. The dielectric layer is formed on the substrate, and is formed with a cavity that is defined by a cavity-defining wall. The electrode is formed in the dielectric layer. The surface modification layer covers the cavity-defining wall, and has a plurality of hydrophobic end groups. The membrane is connected to the dielectric layer, and seals the cavity. The membrane is movable toward or away from the electrode. A method for making a microelectromechanical system device is also provided.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, where the method includes forming an interconnect structure over a first substrate. A dielectric structure is formed over the interconnect structure. The dielectric structure comprises opposing sidewalls defining an opening. A conductive bonding structure is formed on a second substrate. A bonding process is performed to bond the conductive bonding structure to the interconnect structure. The conductive bonding structure is disposed in the opening. The bonding process defines a first cavity between inner opposing sidewalls of the conductive bonding structure and a second cavity between the conducive bonding structure and the opposing sidewalls of the dielectric structure.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.

Abstract: In accordance with embodiments of the present disclosure, a method for forming a structural member may include providing a sheet of structural material and compression molding an in-mold decoration film to a side of the sheet of structural material. In accordance with these and other embodiments of the present disclosure, a method for forming a structural member may include providing a sheet of structural material and adhesively bonding a chassis attachment frame to the sheet of structural material, the chassis attachment frame having one or more attachment features for mechanically coupling the structural member to other one or more other components. In accordance with these and other embodiments of the present disclosure, a method for forming a structural member may include providing a sheet of structural material and molding a chassis attachment frame comprising sheet molding compound to the structural material.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) chip comprising a semiconductor device that is inverted and that overlies a dielectric region inset into a top of a semiconductor substrate. An interconnect structure overlies the semiconductor substrate and the dielectric region and further comprises an intermetal dielectric (IMD) layer. The IMD layer is bonded to the top of the semiconductor substrate and accommodates a pad. A semiconductor layer overlies the interconnect structure, and the semiconductor device is in the semiconductor layer, between the semiconductor layer and the interconnect structure. The semiconductor device comprises a first source/drain electrode overlying the dielectric region and further overlying and electrically coupled to the pad. The dielectric region reduces substrate capacitance to decrease substrate power loss and may, for example, be a cavity or a dielectric layer. A contact extends through the semiconductor layer to the pad.

Abstract: A printed circuit board includes a first and second core. The first core has a first conductive layer, a first non-conductive layer, a first copper layer and a first opening. The first core also has a first solder mask connected to the first copper layer and a first FR4 laminate bonded to the first solder mask. The second core has a second conductive layer, a second non-conductive layer, a second copper layer and a second opening. The second core also has a second solder mask connected to the second copper layer and a second FR4 laminate bonded to the second solder mask. A prepreg layer is between the first copper layer and the second copper layer but not between the first FR4 laminate and the second FR4 laminate.

Abstract: Various embodiments of the present disclosure are directed towards a three-dimensional (3D) trench capacitor, as well as methods for forming the same. In some embodiments, a first substrate overlies a second substrate so a front side of the first substrate faces a front side of the second substrate. A first trench capacitor and a second trench capacitor extend respectively into the front sides of the first and second substrates. A plurality of wires and a plurality of vias are stacked between and electrically coupled to the first and second trench capacitors. A first through substrate via (TSV) extends through the first substrate from a back side of the first substrate, and the wires and the vias electrically couple the first TSV to the first and second trench capacitors. The first and second trench capacitors and the electrical coupling therebetween collectively define the 3D trench capacitor.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device including a conductive bonding structure disposed between a substrate and a MEMS substrate. An interconnect structure overlies the substrate. The MEMS substrate overlies the interconnect structure and includes a moveable membrane. A dielectric structure is disposed between the interconnect structure and the MEMS substrate. The conductive bonding structure is sandwiched between the interconnect structure and the MEMS substrate. The conductive bonding structure is spaced laterally between sidewalls of the dielectric structure. The conductive bonding structure, the MEMS substrate, and the interconnect structure at least partially define a cavity. The moveable membrane overlies the cavity and is spaced laterally between sidewalls of the conductive bonding structure.

Abstract: A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.