Patents by Inventor Xing Wang
Xing Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12360916Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.Type: GrantFiled: September 21, 2023Date of Patent: July 15, 2025Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Fanya Bi, Xing Wang, Hua Tan, Zhe Sun, Bo Yu, Guangyao Han
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Publication number: 20250224877Abstract: Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.Type: ApplicationFiled: January 3, 2025Publication date: July 10, 2025Inventors: Xing Wang, Wenyu Li, Xiaolai Zhu, Xu Zhang
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Patent number: 12332418Abstract: Disclosed herein are methods and systems that use a photonic crystal (PC) for interference scattering microscopy. Incident light is directed onto a surface of the PC and couples into a photonic crystal guided resonance (PCGR) mode of the PC such that less than 1% of the incident light is transmitted through the PC as transmitted light. One or more particles adjacent to the surface of the PC scatter a portion of the light coupled into the PCGR mode as scattered light. An image comprising a pattern of constructive and destructive interference between the transmitted light and the scattered light is formed, and an image sensor may capture one or more image frames of the image. Imaging processing of the one or more image frames can be used to identify at least one scattering center corresponding to at least one particle of the one or more particles.Type: GrantFiled: February 3, 2022Date of Patent: June 17, 2025Assignee: THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOISInventors: Brian T. Cunningham, Nantao Li, Taylor D. Canady, Qinglan Huang, Xing Wang
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Publication number: 20250174285Abstract: Systems, devices, methods, and storage media for managing refreshment of memory cells in memory systems are provided. In one aspect, a memory system includes: a non-volatile memory device including a plurality of memory cells and a memory controller coupled to the non-volatile memory device. The memory controller is configured to: refresh adjacent memory cells of a target memory cell of the plurality of memory cells, when a count of write operations performed on the target memory cell within a preset time duration is greater than a preset threshold.Type: ApplicationFiled: July 1, 2024Publication date: May 29, 2025Inventors: Fanya BI, Xing WANG, Hua TAN, Zhe SUN, Bo YU, Guangyao HAN
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Patent number: 12314577Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.Type: GrantFiled: March 13, 2024Date of Patent: May 27, 2025Assignee: Micron Technology, Inc.Inventors: Xing Wang, Liu Yang, Xiaolai Zhu, Bin Zhao
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Publication number: 20250160253Abstract: Embodiments relate generally to a robotic fruit picking apparatus and a method of picking fruit. An example apparatus includes: a chassis; a robotic arm supported by the chassis and having an end effector, wherein the end effector includes a plurality of grippers and an extendable suction element; a vision system carried by the chassis and configured to identify pieces of fruit for picking; and a control system carried by the chassis and in communication with the vision system to control the robotic arm to pick identified pieces of fruit using the end effector. The control system may be configured to operate in a first mode to control the extendable suction element to extend the suction element towards a piece of fruit. The control system may be further configured to operate in a second mode following the first mode to retain contact with the piece of fruit by applying suction while freely allowing extension or retraction of the suction element based on movement of the piece of fruit.Type: ApplicationFiled: December 21, 2022Publication date: May 22, 2025Applicant: Monash UniversityInventors: Chao Chen, Hongyu ZHOU, Xing WANG, Wesley AU
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Publication number: 20250139658Abstract: A splash advertisement display method and a related device are provided. The method includes: A terminal device displays a splash advertisement; the terminal device detects a first operation of a user, where the first operation is an operation of clicking a preset area; and the terminal device displays a first interface of a first application, where the first interface includes a first advertisement, and content of the first advertisement is related to content of the splash advertisement.Type: ApplicationFiled: October 17, 2022Publication date: May 1, 2025Inventors: Zonglu ZHU, Youqi JIN, Xing WANG, Ming JIANG
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Patent number: 12275109Abstract: A drilling machine tool with a cooling liquid purifying and recycling mechanism. The drilling machine tool comprises a platform in which a blanking hole is formed, wherein air cylinders are fixedly mounted at the top of a transverse plate located above the platform, a lifting plate is mounted after the output shaft ends of the air cylinders penetrate through the transverse plate, an isolation cylinder is arranged below the lifting plate, an opening is formed in the bottom of the isolation cylinder, the bottom end of the vertical shaft slidably penetrates through the isolation cylinder and is fixedly provided with a drill bit, the isolation cylinder is connected with the lifting plate through pressing mechanisms, and a cooling liquid conveying mechanism communicating with the interior of the isolation cylinder is arranged on the platform; and a cooling liquid purifying and recycling mechanism is arranged at the bottom of the platform.Type: GrantFiled: June 8, 2022Date of Patent: April 15, 2025Assignee: North China University of Science and TechnologyInventors: Duo Zhang, Haoqiang Zhang, Xin Jin, Suoxia Hou, Hongyin Zhao, Xinge Wang
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Patent number: 12271870Abstract: Placing an event into a particular cluster can allow various inferences about the event. A new payment transaction that looks similar to a previously identified cluster of mostly fraudulent payment transactions, for example, may be higher risk. The present disclosure includes structural data improvements to the way that online clustering of events (which may include web events and not just payment transactions) occurs. A new event can be classified into a particular segment very quickly using feature table searching, which can allow for better decision making when a short timeframe is required (e.g. transaction processing, online advertising, etc.).Type: GrantFiled: November 16, 2022Date of Patent: April 8, 2025Assignee: PAYPAL, INC.Inventors: Avishay Meron, Xing Wang, Adam Cohen, Chunmao Ran, David Stein
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Patent number: 12265710Abstract: Methods, systems, and devices for memory management procedures for write boost mode are described. A memory system may receive a command to write data. The memory system may write the data to a first location of the memory system using a first mode for storing one bit per memory cell based on receiving the command. The memory system may select a first portion of the data to rewrite to the memory system using a second mode for storing two or more bits per memory cell based on one or more parameters satisfying one or more thresholds. The memory system may write the first portion of the data to a second location of the memory system using the second mode based on selecting the first portion of the data. The memory system may maintain a second portion of the data at the first location of the memory system.Type: GrantFiled: March 16, 2021Date of Patent: April 1, 2025Assignee: Micron Technology, Inc.Inventors: Xing Wang, Zhen Gu, Xu Zhang, Liping Xu
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Publication number: 20250103224Abstract: A memory system includes a memory device including memory cells, and a memory controller coupled to the memory device. A memory cell is configured to be programmed to one of a first state and a second state. The first state corresponds to a first bit, and the second state corresponds to a second bit. The memory controller is configured to receive first data including bits, the bits of the first data including the first bit and the second bit, in response to a second number of the second bit in the first data being larger than a first number of the first bit in the first data, perform a first flipping operation to the first data to obtain a second data including the bits, and store the second data to the memory device.Type: ApplicationFiled: November 13, 2024Publication date: March 27, 2025Inventors: Hua TAN, Xing WANG, Yaolong GAO, Fanya BI, Zhe SUN, Bo YU
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Patent number: 12260094Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.Type: GrantFiled: November 20, 2023Date of Patent: March 25, 2025Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Fanya Bi, Xing Wang, Hua Tan, Zhe Sun, Bo Yu, Guangyao Han
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Publication number: 20250093285Abstract: Provided is a subcellular self-tracer ion imaging and localization method of metal elements. Wherein, the above method includes: using the SEM-FIB-TOF-SIMS system to perform subcellular structure imaging and metal ion imaging on the sample slice, wherein in the SEM-FIB-TOF-SIMS system, the scanning electron microscope (SEM) is used to perform subcellular structure imaging on the sample slice; and the focused ion beam (FIB) is used to perform surface bombardment on the subcellular structures, and the secondary ions excited are detected by the time-of-flight secondary ion mass spectrometry (TOF-SIMS) to obtain the ion information in the analysis area and imaged.Type: ApplicationFiled: December 3, 2024Publication date: March 20, 2025Applicant: Shandong Laboratory of Advanced Agricultural Sciences in WeifangInventors: Xiaohua HUANG, Xing Wang DENG, Mengzhu CHENG, Jun ZHAO, Bin XU
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Patent number: 12255981Abstract: The present disclosure provides methods and apparatuses for implementing high-speed cryptographic operations based on software-hardware collaboration, and electronic devices. In the embodiments of the present disclosure, by analyzing software and hardware computing resources in real-time, the cryptographic device driver allocates the one or more target resources for cryptographic computation to the reference data packets. When the one or more target resources include the target cryptographic device, the cryptographic device executes, according to the characteristics of the target cryptographic algorithm used to perform cryptographic computation on the reference data packet, the acceleration operation corresponding to the target cryptographic algorithm for the cryptographic computation on the reference data packets, such as grouping the reference data packets, to improve a concurrent execution rate of an algorithm and cope with situations with a large amount of service concurrency and data processing.Type: GrantFiled: June 14, 2024Date of Patent: March 18, 2025Assignee: HANGZHOU HIKVISION DIGITAL TECHNOLOGY CO., LTD.Inventors: Bin Wang, Da Chen, Xiaohong Guan, Jiadong Chen, Wei Wang, Xing Wang
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Publication number: 20250086115Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.Type: ApplicationFiled: September 16, 2024Publication date: March 13, 2025Inventors: Xing Wang, Zhen Gu, Xu Zhang, Liping Xu
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Publication number: 20250068886Abstract: Embodiments of this application disclose a method for processing a word sequence using a sequence model and apparatus, to improve a task execution effect of a sequence model. The method includes: encoding a source sequence of words of a first language by using an encoder side of the sequence model, to obtain a first encoding result and a second encoding result; inputting a target sequence of words of the first language, the first encoding result, and the second encoding result into a decoder side of the sequence model to obtain a second sequence of words of a second language, and outputting the second sequence of words in the second language.Type: ApplicationFiled: November 14, 2024Publication date: February 27, 2025Inventors: Zhaopeng TU, Jie HAO, Xing WANG, Longyue WANG
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Publication number: 20250060884Abstract: The present disclosure provides a memory system with a non-volatile memory that includes a plurality of storage areas. Each storage may include a plurality of first storage groups in a first area and a plurality of second storage groups in a second area. The first area may support physical addressing. The second area may not support physical addressing. A memory controller of the memory system may perform a wear leveling process by swapping a first storage group having a first group write count with a second storage group having a second group write count. The first group write count may be a maximum group write count among a plurality of group write counts corresponding to the plurality of first storage groups. The second group write count may be a minimum group write count among a plurality of group write counts corresponding to the plurality of second storage groups.Type: ApplicationFiled: November 20, 2023Publication date: February 20, 2025Inventors: Fanya Bi, Xing Wang, Hua Tan, Zhe Sun, Bo Yu, Guangyao Han
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Patent number: 12223153Abstract: A display panel and a mobile terminal are provided by the present disclosure, including a substrate and a conductive layer on the substrate. The conductive layer includes a plurality of touch electrodes, a plurality of leads, and a plurality of dummy electrodes, wherein each one of the leads is disposed between two adjacent ones of the touch electrodes, and each one of the dummy electrodes is disposed between one of the touch electrodes and one of the leads which are adjacent to each other. Each one of the leads is electrically connected between the corresponding touch electrode and a touch chip, and the dummy electrodes are electrically connected to neither the touch electrodes nor the leads. A shape of a grid structure of the touch electrodes, a shape of a grid structure of the leads, and a shape of a grid structure of the dummy electrodes are the same.Type: GrantFiled: September 14, 2021Date of Patent: February 11, 2025Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.Inventor: Xing Wang
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Patent number: 12216905Abstract: Techniques are described herein for performing a flush operation for a write booster buffer of a memory system. The flush operation may include swapping valid blocks in the write booster buffer for invalid blocks in a storage space of the memory system. After swapping the blocks, the memory system may transfer the information from a first type of blocks that were formerly assigned to the write booster buffer to a second type of blocks in the storage space. In such a flush operation, space is made available in the write booster buffer with less latency than it would take to transfer information between blocks, thereby improving the performance of the write booster mode.Type: GrantFiled: March 19, 2021Date of Patent: February 4, 2025Assignee: Micron Technology, Inc.Inventors: Xing Wang, Wenyu Li, Xiaolai Zhu, Xu Zhang
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Patent number: D1073839Type: GrantFiled: October 19, 2024Date of Patent: May 6, 2025Inventor: Xing Wang