Abstract: A connector having a head that holds a first component and a body connected to the head. The body has a central channel extending along a central axis of the connector, and the central channel receives a fastener. The body has at least two resilient legs. The resilient legs extend obliquely toward the central axis in a direction from the body to the head. The resilient legs engage with the fastener, to attach the connector to the fastener.

Abstract: A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data that includes bits and is to be written into the memory device, counting a first bit number of the bits corresponding to a first state and a second bit number of the bits corresponding to the second state, and in response to the second bit number of the bits being larger than the first bit number of the bits, the flipping operation is performed.

Abstract: The present disclosure provides methods and apparatuses for implementing high-speed cryptographic operations based on software-hardware collaboration, and electronic devices. In the embodiments of the present disclosure, by analyzing software and hardware computing resources in real-time, the cryptographic device driver allocates the one or more target resources for cryptographic computation to the reference data packets. When the one or more target resources include the target cryptographic device, the cryptographic device executes, according to the characteristics of the target cryptographic algorithm used to perform cryptographic computation on the reference data packet, the acceleration operation corresponding to the target cryptographic algorithm for the cryptographic computation on the reference data packets, such as grouping the reference data packets, to improve a concurrent execution rate of an algorithm and cope with situations with a large amount of service concurrency and data processing.

Abstract: Methods, systems, and devices for unmap backlog in a memory system are described. A memory system may be configured to support receiving an unmap command from a host system and signaling, to the host system, an indication that the unmap command has been processed (e.g., handled, acknowledged). In response to the unmap command, the memory system may proceed with various unmap operations, which may include unmapping at least some of the associated addresses after indicating that the unmap command has been processed. For example, a memory system may implement an unmap backlog table to identify sections of addresses that are to be unmapped (e.g., after indicating that the unmap command has been processed). In some examples, the memory system may support various aspects of prioritization between unmap operations (e.g., background unmap operations) and other access operations such as read operations, write operations, or other access operations.

Abstract: An apparatus for real-time monitoring of groundwater level and soil moisture of a gully head landfill area includes: a groundwater observation well set up in a monitoring area; a drop-in liquid level transmitter placed in the groundwater observation well and configured to sense a change of groundwater level and transmit data to an environmental supervision cloud platform (ESCP) through a data collection module; a plurality of soil moisture transmitters arranged in layers on a wall of the groundwater observation well and configured to sense soil moisture; a data collection module configured to receive data from the drop-in liquid level transmitter and transmit the collected signal to an ESCP; and an environmental monitoring host configured to receive data from the soil moisture transmitters and transmit the data to an environmental monitoring cloud platform (EMCP). A user can view real-time data by remotely logging in to the ESCP and EMCP.

Abstract: The present application belongs to the technical field of shooting auxiliary equipment and relates to a shooting bracket, which includes a bracket body, a connection device, a clamping device and an auxiliary handle with a hinged end. The connection device is mounted on the bracket body. One of the bracket body and the auxiliary handle is provided with a first limiting part, and the other is provided with a second limiting part matched the first limiting part. When the auxiliary handle is in the folded state, through meshing the first limiting part and the second limiting part, relative rotation between the auxiliary handle and the bracket body is prevented. The shooting bracket is provided with a first limiting part and a second limiting part that is meshed with each other to limit rotation of the clamping device connected to the connection device.

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping compression techniques are described. A memory system may use an L2P mapping to map logical addresses to physical addresses of the memory system. The L2P mapping may be a hierarchical L2P mapping divided into multiple levels or subsets that are used to identify a physical address corresponding to a logical address. The memory system may write data to a set of physical addresses that are consecutively indexed and may set a flag in an entry of a second-level of the L2P mapping (e.g., of a three-level L2P mapping) to indicate that the entry is associated with a starting physical address of the consecutively indexed physical addresses. The memory system may subsequently read the data starting at the starting physical address based on the flag (e.g., bypassing reading an entry of a lowest-level of the L2P mapping to determine the physical address).

Abstract: An apparatus includes a printed circuit board (PCB), and an integrated circuit (IC) package connected with the PCB. The IC package includes a package substrate, a die secured to the package substrate and including an integrated circuit, and a stiffener ring secured to the package substrate and surrounding so as to define a perimeter around the die. The stiffener ring increases a rigidity of the package substrate and delivers electrical power to the integrated circuit, where the stiffener ring includes a first conductive layer forming a power (PWR) plane for the integrated circuit, a second conductive layer forming a ground (GND) plane for the integrated circuit, and an insulating layer disposed between the first conductive layer and the second conductive layer.

Abstract: The present disclosure involves methods, apparatuses, and computer-readable storage media for media scan in a memory system. In one example, a method for a memory system includes receiving commands from a host coupled to the memory system, wherein the memory system includes a memory device, the memory device includes a memory cell array, and the memory cell array includes a number of memory cells. The method further includes performing operations on the memory device based on the commands. The method further includes scanning at least a group of memory cells of the memory cell array by performing a number of scans within a scan period among the operations.

Abstract: Provided are a method and a system for image batch processing recognition. Improved adaptive threshold segmentation, regional growth segmentation and global threshold segmentation methods are used to recognize red sandstone samples in a process of uniaxial compression failure in a certain area of Yunnan. In an embodiment, batch recognition times and relative errors of partial recognition images are calculated.

Abstract: An example memory controller and readable storage medium are disclosed. An example memory system includes: a non-volatile memory device and a memory controller coupled to the non-volatile memory device; the memory controller is configured to: determine whether data for the logical block address mapping of a received read command belongs to tables of a first class or tables of a second class, and confirm the heat of the data corresponding to the logical block address of the received read command; determine a level of the amount of drift of a threshold voltage of a memory cell corresponding to the logical block address, according to the heat of the data corresponding to the logical block address of the received read command; determine different read voltages that are correspondingly sent to the memory cell corresponding to the logical block address, according to different levels of the amount of drift.

Abstract: In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.

Abstract: In certain aspects, a method for operating a non-volatile memory device is provided. The non-volatile memory device includes memory units. A write count of a first memory unit of the memory units is determined. In response to the write count of the first memory unit reaching one of preset values, a flipped bit count (FBC) of a second memory unit of the memory units that is physically adjacent to the first memory unit is obtained. In response to the FBC of the second memory unit exceeding a threshold, the second memory unit is refreshed.

Abstract: In an example, a memory controller is configured to: check whether a logical block address corresponding to a host read command is maintained in a write buffer; determine a level of an amount of drift corresponding to the logical block address if the logical block address is not maintained in the write buffer, where different levels of the amount of drift correspond to different read voltages; and send a read command to a non-volatile memory device according to the level of the amount of drift corresponding to the logical block address. At least two of the processes of checking whether the logical block address is maintained, determining the level of the amount of drift, or sending the read command are performed in parallel.

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Abstract: A system includes a memory device comprising an array of memory cells coupled with a plurality of page buffers. At least a portion of the array is configured as single-level cell memory. A processing device is coupled to the memory device and includes cache. The processing device detects demand for the cache during a memory operation requiring access to the single-level cell memory. Detecting the demand can include determining an amount of metadata required to be accessed or updated based on a type of the memory operation. The processing device causes, based on the demand, the metadata associated with the memory operation to be moved from one of the cache or the array of memory cells to one or more page buffers of the plurality of page buffers.

Abstract: The present application belongs to the technical field of shooting auxiliary equipment and relates to a shooting bracket, which includes a bracket body, a connection device, a clamping device and an auxiliary handle with a hinged end. The connection device is mounted on the bracket body. One of the bracket body and the auxiliary handle is provided with a first limiting part, and the other is provided with a second limiting part matched the first limiting part. When the auxiliary handle is in the folded state, through meshing the first limiting part and the second limiting part, relative rotation between the auxiliary handle and the bracket body is prevented. The shooting bracket is provided with a first limiting part and a second limiting part that is meshed with each other to limit rotation of the clamping device connected to the connection device.

Abstract: Methods, systems, and devices for dynamic memory management operation are described. A memory system may store data in a first block that includes a first type of memory cells configured to store a single bit of information (e.g., single level cells (SLCs)). The memory system may set a flag associated with the data indicating whether the data includes secure information and is to remain in a block that includes SLCs after a memory management operation (e.g., a garbage collection operation). The memory system may store, as part of the memory management operation for the first block and based on the flag, valid data of the first block in a second block that includes SLCs or a third block that includes a second type of memory cells configured to store two or more bits of information.

Abstract: A method for allocating a data storage space includes detecting one allocation request of an operating system for a continuous storage space for a target program; extracting a feature of the allocation request; determining, based on the feature of the allocation request, a fault tolerance requirement corresponding to the allocation request; and allocating a storage space of a corresponding fault tolerance level to the allocation request based on the fault tolerance requirement corresponding to the allocation request.

Abstract: This application provides a wireless charging coil, and an electronic device and an antenna that include the wireless charging coil. The wireless charging coil includes a plurality of coil groups that are at a plurality of layers and that are connected in series, and an insulation layer that is disposed between two layers of the plurality of coil groups. The wireless charging coil includes a first area and a second area that is disposed at an outer periphery of the first area. A plurality of coil groups disposed in the second area are arranged at the plurality of layers, and each coil group includes a plurality of coils wound in parallel at one layer.