Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to receive a first memory module; a second socket to receive a second memory module; a detachable signal-interconnect; and a memory controller coupled to the detachable signal-interconnect and configured to define a first mode of operation and a second mode of operation, wherein in the first mode of operation the detachable signal-interconnect is to couple the memory-controller to the first memory module and in the second mode of operation the detachable signal-interconnect is to couple the memory controller to the first memory module and the second memory module.

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: The multilayer substrate includes a plurality of layers. Located within the plurality of layers are a number of vias. Conductive traces connect the vias to form trace/via paths having various topologies, geometries, and/or properties.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Abstract: Systems and methods for reducing electrical noise generated during bus turnaround in signal transfer systems are provided. These systems include differential drivers having current sources continuously coupled to a signal bus during all operating modes of the drivers. A first transistor of the driver couples a first signal line of the bus to the driver current source and a second transistor of the driver couples a second signal line of the bus to the driver current source. Each transistor receives control signals in accordance with the operating mode of the driver. These control signals continuously and selectively couple the current source to the bus lines in a manner which provides uniform current distribution across the bus during all driver operating modes. The uniform current distribution across the bus minimizes interruptions in driver current dissipation and any effects from self-induced supply noise during signal transfers.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed in one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.