Abstract: Particular embodiments generally relate to providing risk management. In one embodiment, a first risk is linked to an account group assertion in a data structure. A second risk is linked to a control objective in the data structure. Access to the first risk is granted through the account group's assertion. Access to the second risk is granted through the control objective. Risk management is then performed using the accessed first risk and second risk.

Abstract: An integrated circuit substrate via system, and method of manufacture therefor, includes: a substrate having a substrate via in the substrate; a buffer layer patterned over the substrate via, the buffer layer having a planar surface; and a substrate via cap patterned over the buffer layer, the substrate via cap having a planar surface based on the planar surface of the buffer layer.

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed through the semiconductor wafer. A portion of the semiconductor wafer is removed such that a portion of the conductive via extends above the semiconductor wafer. A first insulating layer is formed over the conductive via and semiconductor wafer. A second insulating layer is formed over the first insulating layer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. A portion of the first and second insulating layers is removed simultaneously from over the conductive via by chemical mechanical polishing (CMP). Alternatively, a first insulating layer including an organic material is formed over the conductive via and semiconductor wafer. A portion of the first insulating layer is removed by CMP. A conductive layer is formed over the conductive via and first insulating layer. The conductive layer is substantially planar.

Abstract: A semiconductor device has a semiconductor wafer and a conductive via formed partially through the semiconductor wafer. A portion of the semiconductor wafer and conductive via is removed by a chemical mechanical polishing process. The semiconductor wafer and conductive via are coplanar at first and second surfaces. A first insulating layer and a second insulating layer are formed over the conductive via and semiconductor wafer. The first insulating layer includes an inorganic material and the second insulating layer includes an organic material. An opening in the first and second insulating layers is formed over the conductive via while a second portion of the conductive via remains covered by the first and second insulating layers. A conductive layer is formed over the conductive via and first insulating layer. An interconnect structure is formed over the conductive layer. The semiconductor wafer is singulated into individual semiconductor die.

Abstract: Data is received that include values that correspond to a plurality of variables. A score is then generated based on the received data and using a boosted ensemble of segmented scorecard models. The boosted ensemble of segmented scorecard models includes two or more segmented scorecard models. Subsequently, data including the score can be provided (e.g., displayed, transmitted, loaded, stored, etc.). Related apparatus, systems, techniques and articles are also described.

Abstract: A semiconductor device has a substrate including a plurality of conductive vias formed vertically and partially through the substrate. An encapsulant is deposited over a first surface of the substrate and around a peripheral region of the substrate. A portion of the encapsulant around the peripheral region is removed by a cutting or laser operation to form a notch extending laterally through the encapsulant to a second surface of the substrate opposite the first surface of the substrate. A first portion of the substrate outside the notch is removed by chemical mechanical polishing to expose the conductive vias. A second portion of the substrate is removed by backgrinding prior to or after forming the notch. The encapsulant is coplanar with the substrate after revealing the conductive vias. The absence of an encapsulant/base material interface and coplanarity of the molded substrate results in less over-etching or under-etching and fewer defects.

Abstract: As part of neural network sensitivity analysis, base outputs of hidden layer nodes of a neural network model for non-perturbed variables can be reused when perturbing the variables. Such an arrangement greatly reduces complexity of the calculations required to generate outputs of the model. Related apparatus, systems, techniques and articles are also described.

Abstract: A tree structure of plurality of information records arranged is recursively grown by splitting at least a portion of the records and by generating at least one predictive model. Related apparatus, systems, methods and computer program products are also described.

Abstract: A mobile device operable in multiple navigation modes and includes navigation devices, a mode selection module, and a power management module. The navigation devices provide respective data associated with at least one of movement, a position, and a location of the mobile device. Each of the navigation devices is individually operable in an active mode and at least one of an inactive mode and a sleep mode. The mode selection module receives the respective data and selects one of the navigation modes based on the data received from one of the navigation devices. Each of the navigation modes corresponds to different ones of the navigation devices operating in the active mode. The power management module, based on the selected one of the navigation modes, transitions the navigation devices between the active mode and the at least one of the inactive mode and the sleep mode.

Abstract: A method of dynamically calculating and updating the Volterra kernels used by the Digital Pre Distortion engine based on output power, input signal bandwidth, multicarrier configuration, frequency response and power amplifier temperature. A dominant Volterra kernels searching DSP engine based on innovation bases with minimum RMS error selection is implemented to continuously update the Volterra kernels set used in DPD to model the power amplifier non linear behaviors.

Abstract: A method of dynamically calculating and updating the Volterra kernels used by the Digital Pre Distortion engine based on output power, input signal bandwidth, multicarrier configuration, frequency response and power amplifier temperature. A dominant Volterra kernels searching DSP engine based on innovation bases with minimum RMS error selection is implemented to continuously update the Volterra kernels set used in DPD to model the power amplifier non linear behaviours.

Abstract: Data is received that characterizes a transaction and includes a plurality of values corresponding to variables. Thereafter, a score is determined for the transaction based on the received data and using a scoring model. The scoring model only uses variables pairs having a divergence residual above a pre-defined threshold. Thereafter, data is provided that characterizes the determined score. Related apparatus, systems, techniques and computer program products are also described.

Abstract: The invention relates to a power grid visualization system and a power grid visualization method based on a three-dimensional geographic information system (GIS) technology. Models to be loaded are divided into different model loading subtasks according to the difference of object types included in a scene to be loaded, and model files are called in parallel from a plurality of subtasks in a multi-thread mode; and meanwhile, on the basis that loading tasks are divided into a plurality of model loading subtasks according to the loaded object types, model files of objects of each type are only read once, moreover, reuse of the model files is not limited to a client loading task, different clients can reuse the read model files, and the characteristics of limited type and relatively consistent specification of power equipment are fully considered, so that rereading of the model files of the same type is avoided.

Abstract: The present invention provides a method and device for treating and analyzing a biological specimen. The biological specimen is introduced into a processing device and treated thermally, mechanically, chemically or any combination thereof within the processing device to alter at least one constitutive characteristic of the biological specimen and to release or create one or more biological indicators from the biological specimen. The biological specimen is further contacted with a treated polymeric material so that at least a portion of the polymeric material binds to the one or more biological indicators.

Abstract: A computer includes an enclosure, and a mainframe module enclosed in the enclosure. The mainframe module includes a base board defining a motherboard, a plurality of drive devices, a heat sink device and a fan thereon. The heat sink device includes a heat sink having a plurality of fins and a heat pipe. The base board is divided into a first part and a second part. The motherboard is located in the first part, and the drive devices are located in the second part. The fan is located between the first and second parts. The heat pipe transmits heat from a heat source on the motherboard to the plurality of fins. The fan blows air to the plurality of fins to cool the heat source on the motherboard.

Abstract: A fan mounting apparatus comprises a computer case having a bottom plate, and a rear plate connected to the bottom plate; the rear plate comprising a flange; the flange comprising a connecting panel extending towards the bottom plate, and a clamping panel extending from the connecting panel towards the bottom plate; a bracket comprising a main body, a clipping portion, and a mounting portion; the clipping portion and the mounting portion are on opposite sides of the main body; the mounting portion comprising a hook; wherein the clipping portion is attached to the bottom plate, the mounting portion is deformable, the hook has a configuration to extend through the clamping panel when the mounting portion is deformed, the clamping panel has a configuration to abut on an outer surface of the hook and is adapted to prevent the bracket from moving away from the rear plate.

Abstract: A computer includes an enclosure, and a mainframe module enclosed in the enclosure. The mainframe module includes a base board defining a motherboard, a plurality of drive devices, a heat sink device and a fan thereon. The heat sink device includes a heat sink having a plurality of fins and a heat pipe. The base board is divided into a first part and a second part. The motherboard is located in the first part, and the drive devices are located in the second part. The fan is located between the first and second parts. The heat pipe transmits heat from a heat source on the motherboard to the plurality of fins. The fan blows air to the plurality of fins to cool the heat source on the motherboard.

Abstract: Particular embodiments generally relate to providing risk management. In one embodiment, a first risk is linked to an account group assertion in a data structure. A second risk is linked to a control objective in the data structure. Access to the first risk is granted through the account group's assertion. Access to the second risk is granted through the control objective. Risk management is then performed using the accessed first risk and second risk.

Abstract: In one embodiment, the invention provides a method for repairing a defective storage device in a physical storage-device array having a plurality of storage devices. The method comprises the steps of identifying a disk error associated with the defective storage device; effecting an error recovery pause based on the disk error; processing one or more outstanding data storage or retrieval requests; and generating a new data storage request instructing the physical disk device array having the defective storage device to store valid data associated with the data storage or retrieval request corresponding to the disk device error, whereby the defective storage device is repaired.

Abstract: In one embodiment, the invention provides a method for accessing a physical storage-device array comprising a plurality of storage devices. The method includes (1) obtaining at least one parameter from a profile selected from two or more profiles concurrently defining two or more virtual arrays, each profile defining (i) a different virtual array associated with a corresponding set of storage devices and (ii) a parameter set of one or more parameters used for accessing the virtual array; and (2) generating an instruction, based on the at least one parameter, for accessing, or disallowing access to, information in the virtual array defined by the selected profile, wherein a parameter in each the parameter set defined by each profile indicates whether two or more storage devices in the corresponding virtual array are degraded.