Patents by Inventor Xinlin Wang

Xinlin Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050189589
    Abstract: Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
    Type: Application
    Filed: February 27, 2004
    Publication date: September 1, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huilong Zhu, Philip Oldiges, Bruce Doris, Xinlin Wang, Oleg Gluschenkov, Huajie Chen, Ying Zhang
  • Patent number: 6924517
    Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.
    Type: Grant
    Filed: August 26, 2003
    Date of Patent: August 2, 2005
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Bruce B. Doris, Philip J. Oldiges, Xinlin Wang, Huilong Zhu
  • Publication number: 20050056937
    Abstract: A connection device includes a plurality of re-configurable vias that connect a first metal layer to a second metal layer. An actuating element is disposed between the first metal layer and the second metal layer. The actuating element changes the configuration of the plurality of re-configurable vias to change the plurality of re-configurable vias between a conductive state and a non-conductive state.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 17, 2005
    Applicant: International Business Machines Corporation
    Inventors: David Frank, Kathryn Guarini, Christopher Murray, Xinlin Wang, Hon-Sum Wong
  • Publication number: 20050045947
    Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETS. The devices have a thin channel, e.g., an ultra-thin (smaller than or equal to 10 nanometers (10 nm)) silicon on insulator (SOI) layer. Source/drain regions are located in recesses at either end of the thin channel and are substantially thicker (e.g., 30 nm) than the thin channel. Source/drain extensions and corresponding source/drain regions are self aligned to the FET gate and thin channel.
    Type: Application
    Filed: August 26, 2003
    Publication date: March 3, 2005
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Huajie Chen, Bruce Doris, Philip Oldiges, Xinlin Wang, Huilong Zhu