Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

Abstract: In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

Abstract: In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.

Abstract: In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the pins. The circuit block may include a ground connection, which may be electrically insulated/electrically separate from the ground connection of other components of the integrated circuit. In an embodiment, the circuit block may include an ESD protection circuit for the pad coupled to the pin. The IC may include another ESD protection circuit for the pad. The circuit block's ESD protection circuit may be sized for the current that may produced within the circuit block for an ESD event, and the IC's ESD protection circuit may be sized for the current that may be produced from the other components of the IC.

Abstract: In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.

Abstract: In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.

Abstract: In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.

Abstract: In an embodiment, an ESD protection circuit is provided in which diodes may be formed between N+ and P+ diffusions within an insulated semiconductor region and in which additional diodes may be formed between adjacent insulated regions of opposite conduction type as well. The diodes may be used in parallel to form an ESD protection circuit, which may have low on resistance and may sink high ESD current per unit area. To support the formation of the ESD protection circuit, each silicon region may have alternating N+ and P+ diffusions, and adjacent silicon regions may have N+ and P+ diffusions alternating in opposite locations. That is a perpendicular drawn between the N+ diffusions of one adjacent region may intersect P+ diffusions in the other adjacent region, and vice versa.

Abstract: Some of the embodiments of the present disclosure provide a transistor comprising a p-type well; and an n-type well; wherein at least a part of one of the p-type well and the n-type well overlaps with at least a part of another of the p-type well and the n-type well. Other embodiments are also described and claimed.

Abstract: A processing technique of electroforming for hard pure gold accessories, including carving waxwork, making silica molding, grafting wax, trimming wax, oiling, electroforming, wax removing and quality inspection, characterized in that LJJAS compounding agent was added to the electrolytic solution, the electroforming temperature is between 50 to 60 degrees, the electroforming speed is 0.05 g/h and pH value of electrolytic solution is between 7.0 to 7.5. Thus, even distribution, strong covering capacity, thin coating, short molding time, big size, lighy weight and high hardness can be achieved. This processing technique is particularly suitable to the gold processing industry.

Abstract: Electrostatic discharge (ESD) devices for protection of integrated circuits are described. ESD devices may be configured to provide uniform breakdown of finger regions extending through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. Such an EDS device may include a collector region having a middle region highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the EDS device. The lightly doped region may be eliminated in the collector region and an interlayer insulating layer is formed in contact with the top side regions and the middle region.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: An electrostatic discharge device may provide better protection of an integrated circuit by more uniform breakdown of a plurality of finger regions. The plurality of finger regions may extend through a first region of a substrate having a first conductivity type and into a second region of the substrate more lightly doped with impurities of the first conductivity type. An electrostatic discharge device may include a collector region having a middle region that may be highly doped with impurities of the first conductivity type. The middle region may be proximate to a layer that is lightly doped with impurities of the first conductivity type and a layer that is doped with impurities of the second conductivity type. The collector region may decrease the breakdown voltage of the electrostatic discharge device.

Abstract: The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically <0.5 pF) and series resistance (typically <0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.