Single Junction Bi-Directional Electrostatic Discharge (ESD) Protection Circuit
In an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.
This application claims benefit of priority to U.S. Provisional Patent application Ser. No. 62/040,129, filed on Aug. 21, 2014. The above application is incorporated herein by reference in its entirety. To the extent that any incorporated material conflicts with the material expressly set forth herein, the expressly set forth material controls.
BACKGROUND1. Technical Field
Embodiments described herein are related to electrostatic discharge (ESD) protection in integrated circuits.
2. Description of the Related Art
The transistors and other circuits fabricated in semiconductor substrates are continually being reduced in size as semiconductor fabrication technology advances. Such circuits are also increasingly susceptible to damage from ESD events, thus increasing the importance of the ESD protection implemented in integrated circuits. Generally, ESD events occur due to the accumulation of static charge, either on the integrated circuits themselves or on devices or other things that come into contact with the integrated circuits. Entities such as humans can also accumulate static charge and cause ESD events when coming into contact with an integrated circuit or its package.
A sudden discharge of the static charge can cause high currents and voltages that can damage the integrated circuit, and the potential for damage is higher with smaller feature sizes. There are various models for ESD events, which integrated circuit designers use to design and evaluate ESD protection circuits. For example, the charged device model (CDM) models the discharge of static electricity accumulated on the integrated circuit itself. The human body model (HBM) models the discharge of static electricity from a human body touch on the integrated circuit. Other models may be used for other types of ESD (e.g. the contact of various machines during manufacturing, etc.).
Typical ESD protection circuits for integrated circuits include diodes that are connected between integrated circuit input/output signal pin connections and power/ground connections. The diodes and other protection circuits are designed to turn on if an ESD event occurs, rapidly discharging the ESD event to avoid damage to the functional circuits (e.g. driver/receiver transistors) that are coupled to the pin connections. The ESD circuits are designed to withstand the maximum currents/voltages of various ESD events, according to a specification to which the integrated circuit is designed.
When a load-sensitive circuit (e.g. a high speed analog circuit) is integrated into a larger integrated circuit, the size of the ESD devices presents significant design challenges. The large ESD devices load the pins, reducing performance of the high speed circuit. The large ESD devices also consume significant area.
SUMMARYIn an embodiment, an ESD protection circuit may include a silicon-controlled rectifier (SCR) and a diode sharing a PN junction and forming a bi-directional ESD circuit. The single PN junction may reduce the capacitive load on the pin, which may allow the high speed circuit to meet its performance goals. In an embodiment, a floating P-well contact may be placed between two neighboring SCRs, to control triggering of the SCRs.
The following detailed description makes reference to the accompanying drawings, which are now briefly described.
While embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include”, “including”, and “includes” mean including, but not limited to.
Various units, circuits, or other components may be described as “configured to” perform a task or tasks. In such contexts, “configured to” is a broad recitation of structure generally meaning “having circuitry that” performs the task or tasks during operation. As such, the unit/circuit/component can be configured to perform the task even when the unit/circuit/component is not currently on. In general, the circuitry that forms the structure corresponding to “configured to” may include hardware circuits. Similarly, various units/circuits/components may be described as performing a task or tasks, for convenience in the description. Such descriptions should be interpreted as including the phrase “configured to.” Reciting a unit/circuit/component that is configured to perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) interpretation for that unit/circuit/component.
This specification includes references to “one embodiment” or “an embodiment.” The appearances of the phrases “in one embodiment” or “in an embodiment” do not necessarily refer to the same embodiment, although embodiments that include any combination of the features are generally contemplated, unless expressly disclaimed herein. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
In one embodiment, the diode 12 and the SCR 14 may share a single junction, and thus may reduce the capacitive load on the pin as compared to dual-diode structures and other ESD structures. For pins that are highly sensitive to capacitance, the ESD protection circuit described herein may provide a lighter load and thus a lower impact on the functional communication on the pin. Examples of pins that are highly sensitive to capacitance may include various high speed input/output (I/O) interfaces such as Peripheral Component Interconnect Express (PCIe), universal serial bus (USB), etc. The diode 12 and the SCR 14 may be formed using the structure illustrated in
The driver/receiver circuitry 20 may include any circuitry to drive and/or receive signals on the pin to which the conductor 18 is connected. If the pin is an output, the circuitry 20 may include driving transistors having source or drain connections to the conductor 18. If the pin is an input, the circuitry 20 may include receiving transistors having gate connections to the conductor 18. If the pin is an input/output pin, the circuitry 20 may include both driving and receiving transistors. The driver/receiver circuitry 20 may include additional ESD protection circuitry (e.g. a voltage clamp circuit).
It is noted that the embodiment of
The fins 34 may be doped with impurities to produce highly doped N-type and P-type conduction regions (denoted as N+ and P+). A highly-doped region may include a greater density of the impurities than the normally doped regions/wells (e.g. P-wells, N-wells, and semiconductor substrate regions). For example, highly-doped regions may include one or more orders of magnitude greater density of impurities than the normally doped regions. In the illustrated embodiment, cross-hatched areas 38 may represent P+ regions and dot-filled areas 40 may represent N+ regions. The areas 38 and 40 may be the areas over which the dopants may be implanted. The fins 34 may actually be separated by insulators such as STI, and so the actual N+ and P+ regions may be in the fins 34 themselves. The N+ and P+ regions may be constructed in areas of the substrate in which diodes and SCRs are to be formed (e.g. to form ESD protection circuits). Depending on the FinFET fabrication process, the fins may be further grown into other shapes such as diamond or merged together through a semiconductor epitaxial process step.
Each semiconductor region 32 may have polysilicon “fingers” built thereon. For example, fingers 36 are illustrated in
The border between each P+ and N+ area forms a P-N junction (more briefly PN junction) that may operate as a diode or may be used as one of the PN junctions of an SCR. Additionally, borders between P-wells and N-wells form PN junctions that may form diodes or SCR junctions. Similarly, borders between P+ areas and N-wells, and borders between N+ areas and P-wells, may form PN junctions. There may be gate-bound diodes/SCRs formed across a region 32 (e.g. the region 32 on the bottom of
It is noted that, in other embodiments, adjacent regions 32 may be entirely of the opposite conduction type (e.g. the P+ area on the top region 32 may be adjacent to another region 32 that is entirely N+). Alternatively, adjacent regions may have the same conduction type. Any combination of various P+ and N+ areas in adjacent regions may be used.
N-wells 30A-30D each include N+ and P+ regions that form transistors for I/O driver/receiver circuits similar to the circuits 20 shown in
The P-Well that includes the P+ VSS region 46 and the N-Well 30A may form a PN junction that may be used as an STI-bound diode 12. The P+ region 44 to the N-well 30A to the P-Well in which the N+ region 48 is formed and finally to the N+ region 48 itself may be PNPN junctions forming the SCR 14. Again, the SCR 14 may be an STI-bound SCR in this embodiment.
The N-well 30A junction to the surrounding P-well may be a single junction that is shared by the diode 12 and the SCR 14 (particularly the cathode of the diode 12 and the anode of the SCR 14), and thus the capacitive load presented by the ESD protection circuit may be low compared to other ESD protection circuits such as dual-diode circuits.
A P+ region 50 in
Lines A-A′ and B-B′ are illustrated in
The N-wells 30E and 30F may include P+ regions for contacts for the driving and/or received signals for the driver/receiver circuits 20, as well as N+ regions coupled to the P+ region 50. The N+ region in the N-wells 30E and 30F may form trigger diodes with the P+ region 50 for the SCRs 14, for embodiments that use trigger diodes to detect ESD events and triggering the SCRs 14. Other embodiments that use other trigger circuits need not include the connections to the N+ regions in the N-wells 30E-30F and may not include the N+ regions in the N-wells 30E-30F either.
The diodes 12 are illustrated across the P-well 30G to N-well 30A boundary and the P-well 30J to N-well 30B boundary. The anodes of the diodes 12 are in the P-wells 30G and 30J and the cathodes of the diodes 12 are in the N-wells 30A and 30B. The SCRs 14 are illustrated from the P+ region 44 to the N-well 30A to the P-well 30H to the N+ region 48, and similarly from the P+ region in the N-well 30B to the N-well 30B to the P-well 30H to the N+ region 48. The anodes of the SCRs 14 are in the N-wells 30A and 30B, and the cathodes of the SCRs 14 are in the P-well 30H. It is noted that, while the arrows illustrating the SCRs 14 extend from one fin of each region to the fin of the adjoining region, each fin of the region may contribute to the SCR 16.
Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.
Claims
1. A FinFET electrostatic discharge (ESD) protection circuit comprising:
- an N-type (N)-well formed in a semiconductor substrate wherein an area around the N-well is a P-type (P)-well forming a PN junction with the N-well;
- a highly-doped P (P+) region formed in the N-well, forming a second PN junction;
- a highly-doped N (N+) region formed in the P-well, forming a third PN junction, wherein the first PN junction, the second PN junction, and the third PN junction form a silicon-controlled rectifier (SCR); and
- a diode formed at another boundary of the P-well and the N-well, wherein the SCR and the diode form a bi-directional ESD protection circuit.
2. The FinFET ESD protection circuit as recited in claim 1 wherein the P+ region in the N-well is coupled to a pin of an integrated circuit including the ESD protection circuit and the N+ region in the P-well is coupled to a ground conductor, and wherein the SCR is forward biased when triggered for an ESD event.
3. The FinFET ESD protection circuit as recited in claim 1 wherein the diode is reverse biased when triggered for an ESD event.
4. The FinFET ESD protection circuit as recited in claim 1 further comprising a second P+ region in the P-well adjacent to the N+ region, wherein the second P+ region provides a floating contact for a trigger input to the SCR.
5. The FinFET ESD protection circuit as recited in claim 4 wherein the second P+ region is isolated from one or more other P+ regions that are coupled to ground contacts.
6. The FinFET ESD protection circuit as recited in claim 4 wherein the floating contact is shared by a plurality of SCRs including the SCR.
7. An integrated circuit comprising:
- a conductor coupled to a pin on a package of the integrated circuit;
- a voltage rail; and
- an electrostatic discharge (ESD) protection circuit coupled between the conductor and the voltage rail wherein the ESD protection circuit comprises: a diode having a first anode coupled to the voltage rail and a first cathode coupled to the pin; and a silicon-controlled rectifier (SCR) having a second cathode coupled to the voltage rail and a second anode coupled to the pin.
8. The integrated circuit as recited in claim 7 wherein the diode is configured to conduct current in response to a first ESD event from the voltage rail to the pin.
9. The integrated circuit as recited in claim 7 wherein the SCR is configured to conduct current in response to a second ESD event from the pin to the voltage rail.
10. The integrated circuit as recited in claim 9 wherein the voltage rail is a ground voltage rail.
11. The integrated circuit as recited in claim 7 wherein the second anode and the first cathode share a PN junction in a semiconductor substrate on which the integrated circuit is fabricated.
12. The integrated circuit as recited in claim 7 wherein the second cathode is coupled to a floating P-well contact for triggering.
13. The integrated circuit as recited in claim 12 further comprising another SCR for another pin, wherein the other SCR is coupled to the floating P-well contact.
14. The integrated circuit as recited in claim 13 further comprising a trigger diode coupled to the floating P-well contact, wherein the trigger diode is configured to trigger the SCR and the other SCR in response an ESD event.
15. The integrated circuit as recited in claim 12 wherein the floating P-well contact does not interfere with a current path of the SCR.
16. An electrostatic discharge (ESD) protection circuit comprising:
- a reverse-biased diode configured to handle a first ESD event between a voltage rail and a pin in an integrated circuit; and
- a forward-biased silicon-controlled rectifier (SCR) configured to handle a second ESD event between the voltage rail and the pin, wherein a first direction of current flow in the first ESD event is opposite a second direction of current flow in the second ESD event.
17. The ESD protection circuit as recited in claim 16 wherein a first node of the reverse-biased diode and a second node of the forward-biased SCR share a PN junction in a semiconductor substrate on which the ESD protection circuit is formed.
18. The ESD protection circuit as recited in claim 17 further comprising a floating P-well contact coupled to a third node of the forward-biased SCR.
19. The ESD protection circuit as recited in claim 17 wherein the voltage rail is a ground voltage rail.
20. The ESD protection circuit as recited in claim 19 wherein the first node is a cathode and the second node is an anode.
Type: Application
Filed: Apr 13, 2015
Publication Date: Feb 25, 2016
Patent Grant number: 9601480
Inventors: Junjun Li (San Jose, CA), Xin Yi Zhang (Cupertino, CA), Xiaofeng Fan (San Jose, CA)
Application Number: 14/684,841